AL-39 pg 31: POINTER REGISTERS (PRn)
PRn.BITNO, as stored in an ITS pair or by SPRPn is six bits. Valid values of 0-35. PRn.BITNO resides in the append unit.
AL-39 pg 32: ADDRESS REGISTERS (ARn)
SARn stores 2 bits of CHAR followed by 4 bits of BITNO.
Al-39 pg 33: This text strongly implies that the 6 bit value is canonical:
NOTE: The reader's attention is directed to the presence of two bit number registers, PRn.BITNO and ARn.BITNO. Because the Multics processor was implemented as an enhancement to an existing design, certain apparent anomalies appear. One of these is the difference in the handling of unaligned data items by the appending unit and decimal unit. The decimal unit handles all unaligned data items with a 9-bit byte number and bit offset within the byte. Conversion from the description given in the EIS operand descriptor is done automatically by the hardware. The appending unit maintains compatibility with the earlier generation Multics processor by handling all unaligned data items with a bit offset from the prior word boundary; again with any necessary conversion done automatically by the hardware. Thus, a pointer register, PRn, may be loaded from an ITS pointer pair having a pure bit offset and modified by one of the EIS address register instructions (a4bd, s9bd, etc.) using character displacement counts. The automatic conversion performed ensures that the pointer register, PR i, and its matching address register, ARi, both describe the same physical bit in main memory.
AL-39, Pg 83 Abbreviations and symbols: This abbreviation is nonsensical, but the abbreviation does not appear in the text
PRn.CHAR Character address register of PRn
AL-39 pg 162: CALL6 sets PR7.BITNO to 0.
AL-39 pg 168: TSPn sets PRn.BITNO to 0.
AL39 pg 172 EAWPn sets PRn.BITNO to TPR.TBR
Al-39 pg 172: EPBPn set PRn.BITNO to 0.
AL-39, pg 173: EPPn sets PRn.BITNO to TPR.TBR.
AL39 pg 173 LPRI sets PRn.BITNO to C(Y-pair)57,62). According to ISOLTS, loading 077 results in the value 037 being loaded.
AL39 pg 1 74 LPRPn sets PRn.BITN t0 C(Y)0,5; faults on C(Y)0,1 == 3.
AL-39 pg 176: SPRI sets C(Y-pair) 57,62 to PRn.BITNO.
AL-39 pg 176: SPRIn sets C(Y-pair) 57,62 to PRn.BITNO.
AL-39 pg 177: SPRPn sets C(Y-pair) 0,5 to PRn.BITNO.
Al-39 pg 178: ADWPn sets PRn.BITNO to 0.
Al-39 pg 219: AARn sets ARn.CHAR, ARn.BITNO.
Al-39 pg 220 LARn sets ARn.CHAR, ARn.BITNO.
AL-39 pg 220 LAREG sets ARn.CHAR, ARn.BITNO
Al-39 pg 220 NARn sets ARn.CHAR, ARn.BITNO.
AL-39 pg 222 ARAn sets ARn.CHAR, ARN.BITNO.
Al-39 pg 222 ARNn set ARn.CHAR, ARn.BITNO.
AL-39 pg 223: SARn sets CY to ARn.CHAR, ARn.BITNO.
AL-39 pg 223: SAREG sets CY-block8[n] to ARn.CHAR, ARn.BITNO.
AL-39 pg 223- 232 : A4BD A6BD, A9BD, ABD, AWD, S4BD, S6BD, S9BD, SBD, SWD: set ARn.CHAR, ARn. BITNO
Al-39 pg 312: When bit 29 of the instruction word is 1, TPR.BITNO is set to PRn.BITNO
AL-39 pg 313: Indirect to Pointer (ITP) Modification: TPR.BITNO is set to odd word bits 21-26
AL-39 pg 314: Indirect to Segment (ITS) Modification: TPR.BITNO is set to odd word bits 21-26
AL-39 pg 317-318: "Character- and Bit-String Addressing"
The processor represents the effective address of a character- or bit-string operand in three different forms as follows: 1. Pointer register form This form consists of a word value (PRn.WORDNO) and a bit value (PRn.BITNO). The word value is the word offset of the word containing the first character or bit of the operand and the bit value is the bit position of that character or bit within the word. This form is seen when C(PRn) are stored as an ITS pointer pair or as a packed pointer (see discussion of ITS pointers earlier in this section and the Store Pointer Register n Packed (sprpn) instruction in Section 4). 2. Address register form This form consists of a word value (ARn.WORDNO), a byte number (ARn.CHAR), and a bit value (ARn.BITNO). The word value is the word offset of the word containing the first character or bit of the operand. The byte number is the number of the 9-bit byte containing the first character or bit. The bit value is the bit position within AR n.CHAR of the first character or bit. This form is seen when C(ARn) are stored with the Store Address Register n (sarn) instruction (see Section 4). 3. Operand Descriptor Form This form is valid for character-string operands only. It consists of a word value (ADDRESS) and a character number (CN). The word value is the word offset of the word containing the first character of the operand and the character number is the number of that character within the word. This form is seen when C(ARn) are stored with the Address Register n to Alphanumeric Descriptor (aran) or Address Register n to Numeric Descriptor (arnn) instructions. (The operand descriptor form for bit-string operands is identical to the address register form.) The terms "pointer register" and "address register" both apply to the same physical hardware. The distinction arises from the manner in which the register is used and in the interpretation of the register contents. "Pointer register" refers to the register as used by the appending unit and "address register" refers to the register as used by the decimal unit. The three forms are compatible and may be freely intermixed. For example, PRn may be loaded in pointer register form with the Effective Pointer to Pointer Register n (eppn) instruction, then modified in pointer register form with the Effective Address to Word/Bit Number of Pointer Register n (eawpn) instruction, then further modified in address register form (assuming character size k) with the Add k-Bit Displacement to Address Register (akbd) instruction, and finally invoked in operand descriptor form by the use of MF.AR in an EIS multiword instruction .