ISOLTS status

ISOLTS status 2016-06-10

Processor report

prom data indicates following system
bytes 0-33
    model      serial     date
    dps8/70m exx            2620

This does not match the serial number and date reported by Multics.

    pm700    test-02b    load &store     bar-000776
    ps702 rev 00a  fixed add-a reg.    102181    
    ps705 rev 00a  fixed add-q reg.    102181
    ps710 rev 00a  fixed add aq reg.   102181
    ps715 rev 00a  fixed add * x-regs  102181
    ps716 rev 00a  fixed add * x-reg.  102181
    ps717 rev 00a  fixed add * x-reg.  102181
    ps720 rev 00a  fixed add to store  102181
    ps721 rev 00a  fixed add to store  102181
    ps722 rev a    fixed add to store  102181
    ps725 rev 00a  shift group         102181
    ps730 rev 00a  fixed mult/div      102281
    ps734 rev 00a  floating add 1      102281
         hangs sometimes?
    ps735 rev 00a  floating add 2      102281
        FSB returns the incorrect result; ISOLTS doesn't prompt after reporting error
    ps736 rev 00a  floating add        102281
        FCMG, FCMP returns an incorrect indicator; ISOLTS doesn't prompt after reporting error
    ps737 rev 00a  floating add        102281
        DFSB returns the incorrect result; ISOLTS doesn't prompt after reporting error
    ps739 rev a    655 floating round  102981
        FRD, FSTR, DFSTR returns the incorrect result; unexpected overflow fault ; ; ISOLTS doesn't prompt after reporting error
    ps740 rev 00a  conditional xfer    102281
    ps745 rev 00a  floating mult/div   102881
        UFM, FMP, FDV, FDI, BCD, GTB, DUFM, DFMP, DFDV, DFDI,  returns the incorrect result; unexpected overflow fault; ISOLTS doesn't prompt after reporting error
    ps750 rev 00a  control register    102181
    ps755 rev b    misc. instructions  042783
    ps760 rev a    index mod. r,ir,ri  103081
    ps762 rev 00a  it mod. & rep ins.  102181
    ps763 rev a    it mod. & rep ins.  103081
    ps764 rev a    it mod.-scr         102981
    ps766 rev a    multilevel mod....  110281
    ps768 rev b    it mod & rep inst.  032786
        RPL fails; ISOLTS doesn't prompt after reporting error
    ps769 rev b    it mod & rep inst.  032786
        RPD LCA LCQ returns incorrect result; ISOLTS doesn't prompt after reporting error
    ps770 rev 00a  misc. logic         103081
        GTB is being used incorrectly by ISOLTS, probably an inappropriate NPL test; ISOLTS doesn't prompt after reporting error
    ps771 rev 00a  hex f.p. t&d 1      102981
        Hex mode floating point not implemented.
    ps772 rev 00a  hex f.p. t&d 2      110281
        Hex mode floating point not implemented.
    ps773 rev 00a  hex f.p. t&d 3      110281
        Hex mode floating point not implemented.
    ps774 rev 00a  hex f.p. t&d 4      110281
        Hex mode floating point not implemented.
    pm776 rev c    6000 fault logic    042783
        NPL tests; not supported.
    ps777 rev a    hex f.p. t&d 5      110381
        Hex mode floating point not implemented.
    ps778 rev 00a  hex f.p. t&d 6      110381
        Hex mode floating point not implemented.
    pm785 rev b       master mode      042783
        Interrupt Inhibit delays interrupt too long.
    ps789 rev a    cpu adder test      100681
    ps791 rev a    ill.procedure flt.  110381
        "unexpected illegal procedure fault"; ISOLTS doesn't prompt after reporting error
    pm792 rev a    ill.procedure flt.  110381
        "unexpected illegal procedure fault "; ISOLTS doesn't prompt after reporting error
    ps800 rev a    cntrl & xfer inst.  110381
    ps805 rev a    address reg tests   110381
    ps808 rev a    eis alphanumerics   110381
        unexpected illegal procedure fault ; ISOLTS doesn't prompt after reporting error
    ps810 rev b    eis numerics        040683
        unexpected lockup error
    ps815 rev a    eis multiply test   110581
        MP3D returns the incorrect results
    ps817 rev a    eis divide test     110581
        DV3D dosen't fault
    ps825 rev d    eis bit strings     101882
    ps830 rev a    edited move group   110581
        unexpected illegal procedure fault
    ps835 rev b    eis misc logic tst  060283
    ps836 rev c    eis misc logic tst  101882
    ps838 rev b    eis mod field test  061683
    ps840 rev a    eis ill. procedure  110581
         dtb faulted incorrectly
    ps841 rev a    eis ill. procedure  110681
        unexpected divide check fault 
    pm842 rev b    eis interrupt       051883
        MLR failed to interrupt; ISOLTS doesn't prompt after reporting error
    ps843 rev a    eis rewrt & align   110681
    ps844 rev 00a   character board    110681
    ps845 rev a     eis reg. test      102181
        unexpected illegal procedure fault -- looks like MVNE MOP; ISOLTS hangs without reporting error
    ps846 rev a     eis adder test     111081
        ps846    test-09a    dec exp test  MP3D

    ps847 rev a     eis btd test       111081
    ps848 rev a     eis dtb test       111081
    ps849 rev a     eis reg. test      111081
        unexpected lockup fault in executive at
        020165 absolute while processing overflow fault
    pa851 rev a    reg inst test no 1  111081
    pa852 rev a    reg inst test no 2  111081
    pa853 rev a    multics instr mods  100681
    pa860 rev a    appending 1         100681
        SDWAM wrong
    pa861 rev b    appending 2         083082
        ABSA returned the incorrect result
    pa862 rev b    appending 3         083082
       hangs?
    pa863 rev b    appending 4         102182
        hangs?
    pa865 rev a        bar mode        100681
        wedges Multics.  CPU FAULT: Fault 1(01), sub 0(00), 'BAR store fault; out of bounds'
    pa866 rev a    64 wd assoc memory  100881
        CAMS either the lru or f/e bits did not clear
    pa867 rev a    64 wd assoc mem 2   022682
        CAMS either the lru or f/e bits did not clear
    pa868 rev a    64 wd assoc memory  110481
        CAMS either the lru or f/e bits did not clear
    pa870 rev a      scu/rcu faults    120381
        Instruction restart missed SDWAM change
    pa875 rev a    eis append test     111081
        MLR return incorrect results
    pa878 rev b    eis faults test     060283
        MLR failed to fault
    pa880 rev a    call & rtcd test    111081
        CALL fail to fault on gate
    pa885 rev a      misc. logic       100981
        unclear
    pa886 rev a       misc logic 2     100981
        extraneous interrupt from location 00
    pa887 rev a       misc. logic      100981
        unexpected illegal procedure fault
    pa890 rev a    multics ill. proc.  100981
        IPR fault returned incorrect IR -- that pesky ABS bit
    pm893 rev a    multics cache memo  072387
        cannot execute without program control of the CMR
    ps905 rev a    random eis test     100681
        unexpected illegal procedure fault
    ps940 rev a    slow/fast store sq  100681
        unexpected access violation fault
    ps945 rev a    mpy & div seq test  100681
        wedges Multics
    ps955 rev f    pas sequence test   112884 
       fail -- complicated

Changes

00f8289 Fix ps805 RPT fail; now RPL fails.
d477776 Fix pm785 RET
f956028 Fix ps808
7a0b89e Fix ps825
e20c5ad Fix ps838 MRL
e20c5ad. Fix ps8815 test 2
a90568aa: DTB: Fix ISOLTS ps840 tst01a bits 0-10 MBZ.
2b0bf78 : Fix ps840 MBZ tests
23cd078ae: Fix ps841

Notes

There is a issue with pm700 and the mode register; the first time isolts is run, the mode register is ok; the 2nd it's not. rebooting resets it.

pm700

************************* hstry reg/mode reg **************************
pm700    test-02n    load &store     bar-000776
***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 103220   patch 106546   subtest loop point 106415

verification of instructions lcpr (tags 03,04,07),
 scpr (tags 00,10,06,20,40) & loading of mode & historyregister.

location 106521  112636452020   instruction is   scpr

prime results     c(y)        c(y+1)        mode
          s/b 000000000000 000000000000 000000000000
          was 000000674003 000000000100 000000000000

function in error - the contents of the hr in loc. sam+6 to sam+9
should be all zeroes in each location.

I believe that the history registers are still collection data during the test and polluting the results;
the collection enable/disable code needs work.

ps734 rev 00a floating add 1 102281

Hangs sometimes

ps735 test-08i fsb test bar-100020

***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 015522   patch 016437   subtest loop point 016430

test t08 checks the fsb instruction.

location 016432  017334575000   instruction is   fsb
c(y) = 005000000000

prime results       a            q       e    ir
          s/b 400000000000 000000000000 240 200200
          was 400000000000 000000000000 240 300200

function in error - execution of the fsb instruction.

hint - max neg. mantissa - positive exponent, 2's compliment produces an overfl
\cow.

UFS testno 70
UFA E 120 A 400000000000 Q 000000000000 Y 005000000000
UFA EAQ -1208925819614629174706176.000000
UFA Y -4.000000
UFA e1 80 m1 400000000000 000000000000
UFA e2 2 m2 400000000000 000000000000
UFA e1 > e2; shift m2 78 right
UFA m2 shifted 777777777777 777777777777
UFA m2 now 000000000000 000000000000
UFA last 1 allones 0 notallzeros 1
UFA e3 80
Sub72b op1 400000000000000000000000 op2 000000000000000000000000 carryin 1 flagsToSet 100000 flags 000200 ovf 0
res 400000000000000000000000
r72 1 r73 1 r74 0 ovf 0 cry 0
UFA IR after add: 100200
UFA returning E 120 A 400000000000 Q 000000000000

Carry is not set and should be

 e1 80 m1 400000000000 000000000000 -  e2 2 m2 400000000000 000000000000

  e 80.   MIN_INT -  e 2 MIN_INT

op2 is much smaller then e1; after normalization, it is 0.

after subtracting 0, borrow should be set; no borrow.

ps736 test-01u fcmg test-1 bar-100010

test start 000376   patch 001505   subtest loop point 001476

test t01 will test part of the fcmg command

location 001501  000230425000   instruction is   fcmg
c(y) = 000777777777

prime results       a       e    ir       c(y)
          s/b 000000000000 200 200200 000777777777
          was 000000000000 200 400200 000777777777
negative indicator should be set
first time g-counter set to 64 in fcmg instruction

ps737 test-08c dfsb test bar-100012

We may have regressed on this one; notes indicate that the expected error is:

***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 005613   patch 006006   subtest loop point 005775

test t08 will test the dfsb command

location 006001  000230577000   instruction is   dfsb
c(y) = 402000100000    c(y+1) = 000000000000

prime results       a            q       e    ir       c(y)
          s/b 340000000000 000000000000 756 000200 402000100000
          was 337777777777 777777774000 756 100200 402000100000
           c(y+1)
    s/b 000000000000
    was 000000000000
execution of dfsb with positive exponent in e reg
and negative exponent from store
no indicators should be set

1c3d76880 23 June shows:

***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 002557   patch 003434   subtest loop point 003425

test 03 will test the fcmp command

location 003430  000230515000   instruction is   fcmp
c(y) = 001000000003

prime results       a       e    ir       c(y)
          s/b 777770000000 034 200200 001000000003
          was 777770000000 034 400200 001000000003

function in error - sign indicator should be set.

hint - checking that sign indicator is set with exponent register
positive and negative compare.

ps737    test-08c    dfsb test       bar-100012
***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 005613   patch 006006   subtest loop point 005775

test t08 will test the dfsb command

location 006001  000230577000   instruction is   dfsb
c(y) = 402000100000    c(y+1) = 000000000000

prime results       a            q       e    ir       c(y)
          s/b 340000000000 000000000000 756 000200 402000100000
          was 337777777777 777777774000 756 100200 402000100000
           c(y+1)
    s/b 000000000000
    was 000000000000

function in error - execution of dfsb with positive exponent in e reg
and negative exponent from store

hint - no indicators should be set

ps737    test-08h    dfsb test       bar-100012
***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 005613   patch 006317   subtest loop point 006306

test t08 will test the dfsb command

location 006312  000230577000   instruction is   dfsb
c(y) = 400000000000    c(y+1) = 000000000000

prime results       a            q       e    ir       c(y)
          s/b 200000000000 000000000000 700 100200 400000000000
          was 200000000000 000000000000 700 000200 400000000000
           c(y+1)
    s/b 000000000000
    was 000000000000

function in error - execution of dfsb with floating point zero from
store

hint - carry indicator should be set

ps739 test-01b rounding ins bar-100006

***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 000377   patch 000505   subtest loop point 000476

testing the frd instruction.

location 000501  000000471000   instruction is   frd
c(y) = 000000000000    c(y+1) = 000000000000

prime results       a            q       e    ir
          s/b 200000000000 000000000000 714 000200
          was 300000000000 000000000000 714 000200
this test will use the frd instruction with a
positive number as data.  the mantissa will not
overflow.
***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 000377   patch 000560   subtest loop point 000551

testing the frd instruction.

location 000554  000000471000   instruction is   frd
c(y) = 000000000000    c(y+1) = 000000000000

prime results       a            q       e    ir
          s/b 200000000000 000000000000 714 177200
          was 400000000000 000000000000 002 337200

function in error - this test will use the frd instruction with a
positive number as data.  the mantissa will not
verflow. all indicators will be set and only
the zero and negative indicators should change

hint - check boards
ps739    test-01d    rounding ins    bar-100006
***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 000377   patch 000625   subtest loop point 000616

testing the frd instruction.

location 000621  000000471000   instruction is   frd
c(y) = 000000000000    c(y+1) = 000000000000

prime results       a            q       e    ir
          s/b 377777777000 000000000000 776 000200
          was 377777777400 000000000000 776 000200

function in error - this test will use the frd instruction with data of
almost all ones.  all the bits in the exponent
register should be set.

hint - check boards
ps739    test-01f    rounding ins    bar-100006
***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 000377   patch 000737   subtest loop point 000730

testing the frd instruction.

location 000733  000000471000   instruction is   frd
c(y) = 000000000000    c(y+1) = 000000000000

prime results       a            q       e    ir
          s/b 400000000000 000000000000 712 200200
          was 400000000000 000000000000 562 200200

function in error - this test will use the frd instruction with a
negative number as data. this will cause k72
  off for a negative mantissa.

hint - check boards
ps739    test-01h    rounding ins    bar-100006
***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 000377   patch 001051   subtest loop point 001042

testing the frd instruction.

location 001045  000000471000   instruction is   frd
c(y) = 000000000000    c(y+1) = 000000000000

prime results       a            q       e    ir
          s/b 400000000000 000000000000 376 214200
          was 400000000000 000000000000 246 214200

function in error - this test will use the frd instruction with the
data and the exponent register set to cause
exponent underflow.

hint - check boards
ps739    test-03a    rounding ins    bar-100006
***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 001335   patch 001403   subtest loop point 001374

testing the fstr instruction.

location 001377  000230470000   instruction is   fstr
c(y) = 777777777777    c(y+1) = 777777777777

prime results       a            q       e    ir       c(y)
          s/b 000000000400 000000000000 000 000200 714400000000
          was 200000000000 000000000000 714 000200 000000000001
           c(y+1)
    s/b 777777777777
    was 777777777777

function in error - this test will use the fstr instruction with a
positive number as data. the mantissa will not
overflow.

hint - check boards
ps739    test-04a    rounding ins    bar-100006
***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 001550   patch 001616   subtest loop point 001607

testing the dfstr instruction.

location 001612  000230472000   instruction is   dfstr
c(y) = 777777777777    c(y+1) = 777777777777

prime results       a            q       e    ir       c(y)
          s/b 000000000000 000000000400 000 000200 604400000000
          was 200000000000 000000000000 604 000200 000000000000
           c(y+1)
    s/b 000000000000
    was 000000000001

function in error - this test will use dfstr instruction with positive
number as data. a non zero normalization should be
preformed.

hint - check boards;
ps739    test-04a    rounding ins    bar-100006
***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 001550   patch 001616   subtest loop point 001607

testing the dfstr instruction.

location 001612  000230472000   instruction is   dfstr
c(y) = 777777777777    c(y+1) = 777777777777

prime results       a            q       e    ir       c(y)
          s/b 000000000000 000000000400 000 000200 604400000000
          was 200000000000 000000000000 604 000200 000000000000
           c(y+1)
    s/b 000000000000
    was 000000000001

function in error - this test will use dfstr instruction with positive
number as data. a non zero normalization should be
preformed.

hint - check boards;
ps739    test-04b    rounding ins    bar-100006
***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 001550   patch 001676   subtest loop point 001667

testing the dfstr instruction.

location 001672  000230472000   instruction is   dfstr
c(y) = 777777777777    c(y+1) = 777777777777

prime results       a            q       e    ir       c(y)
          s/b 000000000000 000000000400 000 177200 604400000000
          was 400000000000 000000000200 002 137200 000000000000
           c(y+1)
    s/b 000000000000
    was 000000000001

function in error - this test will use the dfstr instruction with a
positive number as data. the mantissa will not
overflow. all indicators will be set and only
the zero and negative indicators should change

hint - check boards;
ps739    test-04c    rounding ins    bar-100006
***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
unexpected overflow fault at 001745 relative
calculated absolute address  101744  pr0=000000001737

***********
*** scu ***
***********

prr 0  psr 00000  p 0  fault cntr 1
trr 0  tsr 00000  cpu number 1 delta 00
tsr stat 0000  tbr 00  ic 001744  ir 000200  ca 000230
even instr- 000230472000  odd instr- 000236757000
*** apu status ***
 xsf- 0     sdwm- 0    sd-on- 1     ptwm- 0
pton- 1    pi-ap- 0    dsptw- 0    sdwnp- 0
sdwp- 0      ptw- 0     ptw2- 0      fap- 0
fanp- 1     fabs- 0
*** cu status ***
 rf- 0  rpt- 0  rd- 0  rl- 0
pot- 0  poh- 0  xde- 0  xdo- 0
poa- 0  ic- 0  rst- 0  tag- 00
*** fault data & port status ***    000000000033
0  iro/ish      7   noga  14  amer 20-23 ill act lines
1  oeb/ioc      8   ocb   15  oosb 24-26 ill act ch #
2  e-off/ia-im  9   ocall 16  parl 27-29 connect ch #
3  orb/isp      10  boc   17  paru 30-34 f/i adr 0mod2
4  r-off/ipr    11  inret 18  onc1    35 f/i (1=fault)
5  owb/nea      12  crt   19  onc2
6  w-off/oobb   13  ralr
ps739    test-04c    rounding ins    bar-100006
***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 001550   patch 001750   subtest loop point 001741

testing the dfstr instruction.

location 001744  000230472000   instruction is   dfstr
c(y) = 777777777777    c(y+1) = 777777777777

prime results       a            q       e    ir       c(y)
          s/b 377777777777 777777777600 000 000200 002400000000
          was 377777777777 777777777600 000 000200 777777777777
           c(y+1)
    s/b 000000000000
    was 777777777777
faults         s/b                       was
          none       -------      overflow     - 001745

function in error - this test will use the dfstr instruction with data
that will cause mantissa overflow.

hint - check boards;
ps739    test-04d    rounding ins    bar-100006
***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 001550   patch 002022   subtest loop point 002013

testing the dfstr instruction.

location 002016  000230472000   instruction is   dfstr
c(y) = 777777777777    c(y+1) = 777777777777

prime results       a            q       e    ir       c(y)
          s/b 777777777777 777777777600 000 200200 603000000000
          was 400000000000 000000000000 600 200200 001777777777
           c(y+1)
    s/b 000000000000
    was 777777777777

function in error - this test will use the dfstr instruction with a
negative number as data. this will cause k72
off for a negative mantissa.

hint - check boards;
ps739    test-04f    rounding ins    bar-100006
***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 001550   patch 002146   subtest loop point 002137

testing the dfstr instruction.

location 002142  000230472000   instruction is   dfstr
c(y) = 777777777777    c(y+1) = 777777777777

prime results       a            q       e    ir       c(y)
          s/b 777777777777 777777777600 574 214200 377000000000
          was 400000000000 000000000000 374 214200 575777777777
           c(y+1)
    s/b 000000000000
    was 777777777777

function in error - this test will use the dfstr instruction with the
data and the exponent register set to cause
exponent underflow.

hint - check boards;
ps739    test-04g    rounding ins    bar-100006
***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
unexpected overflow fault at 002215 relative
calculated absolute address  102214  pr0=000000002207

***********
*** scu ***
***********

prr 0  psr 00000  p 0  fault cntr 1
trr 0  tsr 00000  cpu number 1 delta 00
tsr stat 0000  tbr 00  ic 002214  ir 000200  ca 000230
even instr- 000230472000  odd instr- 000236757000
*** apu status ***
 xsf- 0     sdwm- 0    sd-on- 1     ptwm- 0
pton- 1    pi-ap- 0    dsptw- 0    sdwnp- 0
sdwp- 0      ptw- 0     ptw2- 0      fap- 0
fanp- 1     fabs- 0
*** cu status ***
 rf- 0  rpt- 0  rd- 0  rl- 0
pot- 0  poh- 0  xde- 0  xdo- 0
poa- 0  ic- 0  rst- 0  tag- 00
*** fault data & port status ***    000000000033
0  iro/ish      7   noga  14  amer 20-23 ill act lines
1  oeb/ioc      8   ocb   15  oosb 24-26 ill act ch #
2  e-off/ia-im  9   ocall 16  parl 27-29 connect ch #
3  orb/isp      10  boc   17  paru 30-34 f/i adr 0mod2
4  r-off/ipr    11  inret 18  onc1    35 f/i (1=fault)
5  owb/nea      12  crt   19  onc2
6  w-off/oobb   13  ralr
test start 001550   patch 002220   subtest loop point 002211

testing the dfstr instruction.

location 002214  000230472000   instruction is   dfstr
c(y) = 777777777777    c(y+1) = 777777777777

prime results       a            q       e    ir       c(y)
          s/b 777777777777 777777777601 524 400200 400000000000
          was 777777777777 777777777601 524 000200 777777777777
           c(y+1)
    s/b 000000000000
    was 777777777777
faults         s/b                       was
          none       -------      overflow     - 002215

function in error - this test will use the dfstr instruction with data
that will cause the rounding of zeros.

hint - check boards;

ps745 test-01h ufm test bar-100014

***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 000422   patch 001001   subtest loop point 000770

test t 01 checks the ufm instruction

location 000774  000230421000   instruction is   ufm
c(y) = 002400000000

prime results       a            q       e    ir       c(y)
          s/b 000000000000 000377777777 004 000200 002400000000
          was 000000000000 000000777777 004 000200 002400000000
only the first 72 bits are placed in aq reg after
multiply (that h reg is shifting correctly)
ps745    test-01i    ufm test        bar-100014
***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 000422   patch 001032   subtest loop point 001021

test t 01 checks the ufm instruction

location 001025  000230421000   instruction is   ufm
c(y) = 002400000000

prime results       a            q       e    ir       c(y)
          s/b 000000000000 000777777777 004 000200 002400000000
          was 000000000000 000001777777 004 000200 002400000000

function in error - check that h reg is being shifted correctly
ps745    test-01m    ufm test        bar-100014
***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 000422   patch 001216   subtest loop point 001205

test t 01 checks the ufm instruction

location 001211  000230421000   instruction is   ufm
c(y) = 002400000000

prime results       a            q       e    ir       c(y)
          s/b 100000000000 000000000000 400 020200 002400000000
          was 200000000000 000000000000 376 020200 002400000000
faults         s/b                       was
        overflow     -001212      overflow     - 001212

function in error - exponent overflow should set when exponent exceeds
+127
test start 000422   patch 001435   subtest loop point 001424

test t 01 checks the ufm instruction

location 001430  000230421000   instruction is   ufm
c(y) = 002000000001

prime results       a            q       e    ir       c(y)
          s/b 000000000000 000100000000 004 000200 002000000001
          was 000000000000 000000200000 004 000200 002000000001

function in error - h reg shifting correctly
test start 000422   patch 001474   subtest loop point 001463

test t 01 checks the ufm instruction

location 001467  000230421000   instruction is   ufm
c(y) = 002500000000

prime results       a            q       e    ir       c(y)
          s/b 540000000000 000000000000 004 240200 002500000000
          was 660000000000 000000000000 006 240200 002500000000

function in error - normalization due to overflow
test start 000422   patch 001535   subtest loop point 001524

test t 01 checks the ufm instruction

location 001530  000230421000   instruction is   ufm
c(y) = 006765432100

prime results       a            q       e    ir       c(y)
          s/b 012170533472 754334727543 376 000200 006765432100
          was 012170533472 165730671656 376 000200 006765432100

function in error - insure proper multiplication of number
test start 001613   patch 001757   subtest loop point 001746

test t 02 checks the fmp instruction

location 001752  000230461000   instruction is   fmp
c(y) = 020100000000

prime results       a            q       e    ir       c(y)
          s/b 200000000000 000000000000 064 000200 020100000000
          was 200000000000 000000000000 044 000200 020100000000

function in error - normalization of 71 bits and decrementing of "e"
reg
test start 001613   patch 002014   subtest loop point 002003

test t 02 checks the fmp instruction

location 002007  000230461000   instruction is   fmp
c(y) = 020100000000

prime results       a            q       e    ir       c(y)
          s/b 200000000000 000000000000 410 020200 020100000000
          was 200000000000 000000000000 376 020200 020100000000
faults         s/b                       was
        overflow     -002010      overflow     - 002010

function in error - exponent overflow setting when "e" reg exceeds +127
test start 002401   patch 002702   subtest loop point 002671

test t 03 checks the fdv instruction

location 002675  000230565000   instruction is   fdv
c(y) = 002300000000

prime results       a            q       e    ir       c(y)
          s/b 252525252525 000000000000 006 000200 002300000000
          was 252525252522 000000000000 006 000200 002300000000

function in error - correct shifting of n-reg and proper division of
resulting mantissa
unexpected overflow fault at 002774 relative
calculated absolute address  102773  pr0=000000002765

***********
*** scu ***
***********

prr 0  psr 00000  p 0  fault cntr 1
trr 0  tsr 00000  cpu number 1 delta 00
tsr stat 0000  tbr 00  ic 002773  ir 020200  ca 000230
even instr- 000230565000  odd instr- 000230565000
*** apu status ***
 xsf- 0     sdwm- 0    sd-on- 1     ptwm- 0
pton- 1    pi-ap- 0    dsptw- 0    sdwnp- 0
sdwp- 0      ptw- 0     ptw2- 0      fap- 0
fanp- 1     fabs- 0
*** cu status ***
 rf- 0  rpt- 0  rd- 0  rl- 0
pot- 0  poh- 0  xde- 0  xdo- 0
poa- 0  ic- 0  rst- 0  tag- 00
*** fault data & port status ***    000000000033
0  iro/ish      7   noga  14  amer 20-23 ill act lines
1  oeb/ioc      8   ocb   15  oosb 24-26 ill act ch #
2  e-off/ia-im  9   ocall 16  parl 27-29 connect ch #
3  orb/isp      10  boc   17  paru 30-34 f/i adr 0mod2
4  r-off/ipr    11  inret 18  onc1    35 f/i (1=fault)
5  owb/nea      12  crt   19  onc2
6  w-off/oobb   13  ralr

ps768 fails at RPL

was:

repeat link (rpl) instruction test.

location 004534  004300500200   instruction is   rpl
location 004535  000513075012   instruction is   ada,2

prime results   x0     x2         a        ic     ir
          s/b 000300 000514 000000000002 004537 002200
          was 000300 000514 000514000002 004537 002200
repeat link (rpl) count test -rpl an ada

now:

test start 004370   patch 004465   subtest loop point 004454

repeat link (rpl) instruction test.

location 004460  000100500200   instruction is   rpl
location 004461  000512235011   instruction is   lda,1

prime results   x0     x1         a        ic     ir
          s/b 000100 000513 000000000002 004463 002200
          was 000100 000512 000513000001 004463 002200

function in error - repeat link confidence test -rplx a lda

hint         probable faulty;
test start 004370   patch 004541   subtest loop point 004531

repeat link (rpl) instruction test.

location 004534  002300500200   instruction is   rpl
location 004535  000513075012   instruction is   ada,2

prime results   x0     x2         a        ic     ir
          s/b 000300 000513 000000000001 004537 002200
          was 000300 000513 000514000001 004537 002200

function in error - repeat link (rpl) count test -rpl an ada

hint         probable faulty

In order to get the first RPL test to pass, a hack was needed:

// Wierd RPL hack. ISOLTS expects the CY link address to be set to zero on TRO,
// but the tally isn't decremented until after the instruction executes.
//
// Workaround: If the tally is 1 (PTRO), force the condition.
    if (cpu.cu.rl && getbits18 (cpu.rX [0], 0, 8) == 1)
      {
sim_printf ("RL workaround\n");
        putbits36 (& cpu.CY, 0, 18, 0);
      }

The sequence of repeat events in the emulator may not match the hardware; probably much of the X register manipulation happened
in parallel with the instruction execution.

ps769 test-01f bar-100010

***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 000751   patch 002610   subtest loop point 002570

repeat double instruction test

location 002575  003600560200   instruction is   rpd
location 002576  000516335011   instruction is   lca,1
location 002577  000434336032   instruction is   lcq,2*

prime results   x0     x1     x2         a            q        ic
          s/b 001600 000516 000434 070707070710 070707070710 002601
          was 001600 000516 000434 070707070710 000000000000 002601
          ir
    s/b 002200
    was 002200
rpd the pair lca, lcq using ri modification.

ps770 test-01l z comparator bar-100016

***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 000425   patch 001174   subtest loop point 001117

testing the z comparator

location 001170  000000774000   instruction is   gtb

prime results   x1         a
          s/b 001170 777777777777
          was 601171 600000000000
this test is testing the z function with the
gray to binary instruction.

pm776 connect test

pm776    test-02a    connect test    bar-000776
***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 101326   patch 101425   subtest loop point 101371

verifying connect fault functions properly.

location 101373  100403015000   instruction is   cioc

prime results       a
          s/b 101376000000
          was 101374000000
faults         s/b                       was
        connect      -101376        none       - ------

function in error - tests the connect fault in master mode.
cioc issued to control processor from odd location.
   c(a-reg) = ic fault address.

hint - the "connect" fault must occur within "ic+2".
probable error board-
pm776    test-04a    timer runout    bar-000776
***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 102242   patch 102300   subtest loop point 102263

checking timer runout fault functions properly.

location 102274  102275715000   instruction is   tss

faults         s/b                       was
      timer-run-out  -102276        none       - ------

function in error - verifies the timer runout fault in master mode
is not recognized until processor is in slave mode.
 slave mode set from an even location.
************************* 6000 fault logic   **************************
pm776    test-04f    timer runout    bar-000776
***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 102242   patch 102524   subtest loop point 102513

checking timer runout fault functions properly.

faults         s/b                       was
      timer-run-out  -102522        none       - ------

function in error - the timer runs out in master mode and then
a mme fault is caused before going to slave mode.
then check for a timer runout fault.

hint - probable error board-
pm776    test-04g    timer runout    bar-000776
***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 102242   patch 102577   subtest loop point 102561

checking timer runout fault functions properly.

faults         s/b                       was
        lockup       -102570        none       - ------

function in error -
testing for lockup fault by executing a "xed" from
an odd location followed by a "tra *-1".

hint - probable error board-
refer to co # phaopg124.
pm776    test-08a    lockup test     bar-000776
***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 104055   patch 104172   subtest loop point 104107

verifying lockup fault functions properly.

location 104123  104122601200   instruction is   tnz

prime results    tr
          s/b 000000000
          was 000013124
faults         s/b                       was
        lockup       -104123        none       - ------

function in error -
after setting the slave mode lockup time at
2  milliseconds an uninterruptable two
 instruction loop is entered while in master
mode.  a check is made for the 32 mil. master
mode lockup time being with 3 counts
(3/512 milliseconds) plus or minus, 4 counts
(4/512 milliseconds) if dps-e.  the timer
register contains the number of counts the
lockup timer was off.
pm776    test-08b    lockup test     bar-000776
***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 104055   patch 104300   subtest loop point 104215

verifying lockup fault functions properly.

location 104231  104230601200   instruction is   tnz

prime results    tr
          s/b 000000000
          was 000013124
faults         s/b                       was
        lockup       -104231        none       - ------

function in error -
after setting the slave mode lockup time at
4  milliseconds an uninterruptable two
 instruction loop is entered while in master
mode.  a check is made for the 32 mil. master
mode lockup time being with 3 counts
(3/512 milliseconds) plus or minus, 4 counts
(4/512 milliseconds) if dps-e.  the timer
register contains the number of counts the
lockup timer was off.
pm776    test-08c    lockup test     bar-000776
***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 104055   patch 104406   subtest loop point 104323

verifying lockup fault functions properly.

location 104337  104336601200   instruction is   tnz

prime results    tr
          s/b 000000000
          was 000013125
faults         s/b                       was
        lockup       -104337        none       - ------

function in error -
after setting the slave mode lockup time at
8  milliseconds an uninterruptable two
 instruction loop is entered while in master
mode.  a check is made for the 32 mil. master
mode lockup time being with 3 counts
(3/512 milliseconds) plus or minus, 4 counts
(4/512 milliseconds) if dps-e.  the timer
register contains the number of counts the
lockup timer was off.
pm776    test-08d    lockup test     bar-000776
***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 104055   patch 104513   subtest loop point 104431

verifying lockup fault functions properly.

location 104445  104444601200   instruction is   tnz

prime results    tr
          s/b 000000000
          was 000013125
faults         s/b                       was
        lockup       -104445        none       - ------

function in error -
after setting the slave mode lockup time at
16 milliseconds an uninterruptable two
 instruction loop is entered while in master
mode.  a check is made for the 32 mil. master
mode lockup time being with 3 counts
(3/512 milliseconds) plus or minus, 4 counts
(4/512 milliseconds) if dps-e.  the timer
register contains the number of counts the
lockup timer was off.
pm776    test-08e    lockup test     bar-000776
***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 104055   patch 104642   subtest loop point 104543

verifying lockup fault functions properly.

location 104571  104570601000   instruction is   tnz

prime results    tr
          s/b 000000000
          was 777755124
faults         s/b                       was
        lockup       -104571        none       - ------

function in error - after setting the lockup time at 2 milliseconds,
a two instruction loop is entered while in slave
  mode.  a check is made for the lockup time being
    within 5 counts(5/512 milliseconds) plus or minus. the
timer register contains the number of counts the
  lockup timer was off.
pm776    test-08f    lockup test     bar-000776
***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 104055   patch 104772   subtest loop point 104672

verifying lockup fault functions properly.

location 104721  104720601000   instruction is   tnz

prime results    tr
          s/b 000000000
          was 777757125
faults         s/b                       was
        lockup       -104721        none       - ------

function in error - after setting the lockup time at 4 milliseconds,
a two instruction loop is entered while in slave
  mode.  a check is made for the lockup time being
    within 5 counts(5/512 milliseconds) plus or minus. the
timer register contains the number of counts the
  lockup timer was off.
location 105051  105050601000   instruction is   tnz

prime results    tr
          s/b 000000000
          was 777763125
faults         s/b                       was
        lockup       -105051        none       - ------

function in error - after setting the lockup time at 8 milliseconds,
a two instruction loop is entered while in slave
  mode.  a check is made for the lockup time being
    within 5 counts(5/512 milliseconds) plus or minus. the
timer register contains the number of counts the
  lockup timer was off.
location 105201  105200601000   instruction is   tnz

prime results    tr
          s/b 000000000
          was 777773125
faults         s/b                       was
        lockup       -105201        none       - ------

function in error - after setting the lockup time at 16 milliseconds,
a two instruction loop is entered while in slave
  mode.  a check is made for the lockup time being
    within 5 counts(5/512 milliseconds) plus or minus. the
timer register contains the number of counts the
  lockup timer was off.
unexpected lockup fault at 105303 absolute

***********
*** scu ***
***********

prr 0  psr 00000  p 1  fault cntr 1
trr 0  tsr 00000  cpu number 1 delta 00
tsr stat 0000  tbr 00  ic 105302  ir 000220  ca 105302
even instr- 105302710000  odd instr- 105304710000
*** apu status ***
 xsf- 0     sdwm- 0    sd-on- 1     ptwm- 0
pton- 1    pi-ap- 0    dsptw- 0    sdwnp- 0
sdwp- 0      ptw- 0     ptw2- 0      fap- 0
fanp- 0     fabs- 1
*** cu status ***
 rf- 0  rpt- 0  rd- 0  rl- 0
pot- 0  poh- 0  xde- 0  xdo- 0
poa- 0  ic- 0  rst- 1  tag- 00
*** fault data & port status ***    000000000017
0  iro/ish      7   noga  14  amer 20-23 ill act lines
1  oeb/ioc      8   ocb   15  oosb 24-26 ill act ch #
2  e-off/ia-im  9   ocall 16  parl 27-29 connect ch #
3  orb/isp      10  boc   17  paru 30-34 f/i adr 0mod2
4  r-off/ipr    11  inret 18  onc1    35 f/i (1=fault)
5  owb/nea      12  crt   19  onc2
6  w-off/oobb   13  ralr
test start 104055   patch 105303   subtest loop point 105266

verifying lockup fault functions properly.

location 105302  105302710000   instruction is   tra

faults         s/b                       was
        lockup       -105302      lockup       - 105303

function in error - tests for lockup fault in master mode
   by executing a "tra to self" instruction from an
even location.

pm785 Interrupt Inhibit delays interrupt too long

tests the interrupt inhibit bit

location 103050  010000637207   instruction is   ldt,dl

prime results   ic
          s/b 103062
          was 103062
faults         s/b                       was
      timer-run-out  -103060    timer-run-out  - 103062
DBG(2411935279)> CPU1 TRACE: 00000|103055 000000235207 (LDA 000000,DL) 000000 235(0) 0 1 0 07

DBG(2411935283)> CPU1 TRACE: 00000|103056 000000235207 (LDA 000000,DL) 000000 235(0) 0 1 0 07

inhibit off, odd instruction

DBG(2411935287)> CPU1 TRACE: 00000|103057 000000235007 (LDA 000000,DL) 000000 235(0) 0 0 0 07

inhibit off, even instruction; ISOLTS expects us to fault here
DBG(2411935291)> CPU1 TRACE: 00000|103060 100242554000 (STC1 100242) 100242 554(0) 0 0 0 00

DBG(2411935295)> CPU1 TRACE: 00000|103061 111113235000 (LDA 111113) 111113 235(0) 0 0 0 00

DBG(2411935297)> CPU1 FAULT: Fault 4(04), sub 0(00), dfc N, 'Timer runout'
DBG(2411935297)> CPU1 FAULT: 00000|103062 111113235000 (LDA 111113) 111113 235(0) 0 0 0 00

When I read AL39, I interpreted "fetching instructions in pairs as being even/odd pairs; if it is the case that it
would fetch odd/even pairs, then the above code sequence makes sense.

'wasInhibited' would mean either of the last two instructions fetched, not the last even/odd pair.

ps791 test-03a ill.sequence bar-100012

***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
unexpected illegal procedure fault at 007132 relative
calculated absolute address  107131  pr0=000000007122

***********
*** scu ***
***********

prr 0  psr 00000  p 0  fault cntr 1
trr 0  tsr 00000  cpu number 1 delta 00
tsr stat 0000  tbr 00  ic 007131  ir 735200  ca 007131
even instr- 001600560200  odd instr- 000270754000
*** apu status ***
 xsf- 0     sdwm- 0    sd-on- 1     ptwm- 0
pton- 1    pi-ap- 0    dsptw- 0    sdwnp- 0
sdwp- 0      ptw- 0     ptw2- 0      fap- 0
fanp- 1     fabs- 0
*** cu status ***
 rf- 0   rpt- 0  rd- 0   rl- 0
pot- 0  poh- 0  xde- 0  xdo- 0
poa- 0  ic- 0  rst- 0  tag- 00
*** fault data & port status ***    100000000025

This translates to 'rpd/sti' caused an illegal procedure fault.

Allowing STI in RPX leads to

test start 006267   patch 006746   subtest loop point 006716

test the function of the illegal procedure fault
to detect and trap illegal instruction sequences.

location 006721  000200560211   instruction is   rpd
location 006722  000230754000   instruction is   sti

prime results   x0     x1     x2     x3     x4     x5     x6     x7
          s/b 000200 277777 277777 277777 277777 277777 277777 277777
          was 000200 277777 277777 277777 277777 277777 277777 277777
              a            q       e    ir       c(y)        c(y+1)
    s/b 000000000000 000000000000 276 735200 006723710000 777777777777
    was 000000000000 000000000000 276 735200 006723710000 777777777777
            fault      register
    s/b 240000000000 000000000000
    was 200000000000 000000000000
faults         s/b                       was
   illegal procedure -006723 illegal procedure - 006723

function in error - the attempt to repeat a  sti  instruction
should have faulted; registers and storage remained unaltered.

This says STI is not allowed in RPD.

pm792 test-03a ill.sequence bar-000000

***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
unexpected illegal procedure fault at 107144 absolute

***********
*** scu ***
***********

prr 0  psr 00000  p 1  fault cntr 1
trr 0  tsr 00000  cpu number 1 delta 11
tsr stat 0000  tbr 00  ic 107143  ir 135220  ca 100230
even instr- 100230020017  odd instr- 100270754000
*** apu status ***
 xsf- 0     sdwm- 0    sd-on- 1     ptwm- 0
pton- 1    pi-ap- 0    dsptw- 0    sdwnp- 0
sdwp- 0      ptw- 0     ptw2- 0      fap- 0
fanp- 0     fabs- 1
*** cu status ***
 rf- 0   rpt- 0  rd- 0   rl- 0
pot- 0  poh- 0  xde- 0  xdo- 0
poa- 0  ic- 0  rst- 0  tag- 00
*** fault data & port status ***    000000000025
0  iro/ish      7   noga  14  amer 20-23 ill act lines
1  oeb/ioc      8   ocb   15  oosb 24-26 ill act ch #
2  e-off/ia-im  9   ocall 16  parl 27-29 connect ch #
3  orb/isp      10  boc   17  paru 30-34 f/i adr 0mod2
4  r-off/ipr    11  inret 18  onc1    35 f/i (1=fault)
5  owb/nea      12  crt   19  onc2
6  w-off/oobb   13  ralr

ps808 test-04c alphanumeric bar-100016

***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
unexpected illegal procedure fault at 004205 relative
calculated absolute address  104205  pr0=000000010030

***********
*** scu ***
***********

prr 0  psr 00000  p 0  fault cntr 1
trr 0  tsr 00000  cpu number 1 delta 00
tsr stat 0000  tbr 00  ic 004205  ir 000240  ca 004207
even instr- 777000106600  odd instr- 777000106600
*** apu status ***
 xsf- 0     sdwm- 0    sd-on- 1     ptwm- 0
pton- 1    pi-ap- 0    dsptw- 0    sdwnp- 0
sdwp- 0      ptw- 0     ptw2- 0      fap- 0
fanp- 1     fabs- 0
*** cu status ***
 rf- 0  rpt- 0  rd- 0  rl- 0
pot- 0  poh- 0  xde- 0  xdo- 0
poa- 0  ic- 0  rst- 0  tag- 00
*** fault data & port status ***    000000000025
0  iro/ish      7   noga  14  amer 20-23 ill act lines
1  oeb/ioc      8   ocb   15  oosb 24-26 ill act ch #

ps810 test-01i eis numerics bar-10001

After 80 MVN tests:

isolts error message sequence # 0 logged at 06/24/16  1135.8 pst Fri for cpu b 
\cusing memory b

************************* eis numerics       **************************
ps810    test-01l    eis numerics    bar-100014
***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
unexpected lockup fault at 024664 absolute

***********
*** scu ***
***********

prr 0  psr 00000  p 1  fault cntr 1
trr 0  tsr 00000  cpu number 1 delta 00
tsr stat 0000  tbr 00  ic 024663  ir 144220  ca 024663
even instr- 024663710200  odd instr- 024663710200
*** apu status ***
 xsf- 0     sdwm- 0    sd-on- 1     ptwm- 0
pton- 1    pi-ap- 0    dsptw- 0    sdwnp- 0
sdwp- 0      ptw- 0     ptw2- 0      fap- 0
fanp- 0     fabs- 1
*** cu status ***
 rf- 0  rpt- 0  rd- 0  rl- 0
pot- 0  poh- 0  xde- 0  xdo- 0
poa- 0  ic- 0  rst- 1  tag- 00
*** fault data & port status ***    000000000017
0  iro/ish      7   noga  14  amer 20-23 ill act lines
1  oeb/ioc      8   ocb   15  oosb 24-26 ill act ch #
2  e-off/ia-im  9   ocall 16  parl 27-29 connect ch #
3  orb/isp      10  boc   17  paru 30-34 f/i adr 0mod2
4  r-off/ipr    11  inret 18  onc1    35 f/i (1=fault)
5  owb/nea      12  crt   19  onc2
6  w-off/oobb   13  ralr

ps815 mp3d wrong

************************* eis multiply test  **************************
ps815    test-03b    mp3d test 3     bar-100016
***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 003424   patch 003607   subtest loop point 003556

tests the multiplicand shift alignment calculation.

location 003564  000000226600   instruction is   mp3d
location 003565  010230030077   descriptor word
location 003566  010250030077   descriptor word
location 003567  010270030077   descriptor word

prime results   ir
          s/b 044200
          was 044200

function in error - tests a multiplicand shift alignment of 33 digits.
shift count = #leading zeroes - 1.

c(string 1) =
relocatable memory
110230   010230  062062062062  062062062062  062062062062  062062062062  062062
\c062062  062062062062  062062062062  062062062062
110240   010240  062062062062  062062062062  062062062062  062062062062  062062
\c062062  062062062062  062062062062  062062062062

c(string 2) =
relocatable memory
110250   010250  060060060060  060060060060  060060060060  060060060060  060060
\c060060  060060060060  060060060060  060060060060
110260   010260  060061060060  060060060060  060060060060  060060060060  060060
\c060060  060060060060  060060060060  060060060060

s/b  c(string 3) =
relocatable memory
112270   012270  062062062062  062062062062  062062062062  062062062062  062062
\c062062  062062062062  062062062062  062062062062
112300   012300  062062060060  060060060060  060060060060  060060060060  060060
\c060060  060060060060  060060060060  060060060060

was  c(string 3) =
relocatable memory
110270   010270  062062062062  062062062062  062062062062  062062062062  062062
\c062062  062062062062  062062062062  062062062062
110300   010300  062062062062  062062062062  062062062062  062062060060  060060
\c060060  060060060060  060060060060  060060060060

            *** words in error      8, 9, 10, 11,

ps817 dv3d doesn't fault.

***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 000534   patch 000737   subtest loop point 000701

testing the dv3d instruction divide check faults

location 000707  000000227600   instruction is   dv3d
location 000710  010450030001   descriptor word
location 000711  010470030077   descriptor word
location 000712  010510037477   descriptor word

prime results   ir
          s/b 000240
          was 000200
faults         s/b                       was
      divide check   -000710        none       - ------
the calculated length of the quotient is > 64;
the divide check fault should have occurred.

The NQ check is not performed.

ISOLTS: "the calculated length of the quotient is > 64; the divide check fault should have occurred."

AL39: "If C(Y-charn1) = decimal 0 or NQ > 63, then division does not take place, C(Y-charn3) are unchanged, and a divide check fault occurs."

The code:

    // TODO: Need to check/implement this
    // The number of required quotient digits, NQ, is determined before
    // division begins as follows:

ps830 test-01a mve-ar-modif bar-100022

***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
unexpected illegal procedure fault at 000664 relative
calculated absolute address  100664  pr0=000000000000

***********
*** scu ***
***********

prr 0  psr 00000  p 0  fault cntr 1
trr 0  tsr 00000  cpu number 1 delta 00
tsr stat 0000  tbr 00  ic 000664  ir 400240  ca 000741
even instr- 000000020700  odd instr- 100752000014
*** apu status ***
 xsf- 0     sdwm- 0    sd-on- 1     ptwm- 0
pton- 1    pi-ap- 0    dsptw- 0    sdwnp- 0
sdwp- 0      ptw- 0     ptw2- 0      fap- 0
fanp- 1     fabs- 0
*** cu status ***
 rf- 0  rpt- 0  rd- 0  rl- 0
pot- 0  poh- 0  xde- 0  xdo- 0
poa- 0  ic- 0  rst- 0  tag- 00
*** fault data & port status ***    000000000025
0  iro/ish      7   noga  14  amer 20-23 ill act lines
1  oeb/ioc      8   ocb   15  oosb 24-26 ill act ch #
2  e-off/ia-im  9   ocall 16  parl 27-29 connect ch #
3  orb/isp      10  boc   17  paru 30-34 f/i adr 0mod2
4  r-off/ipr    11  inret 18  onc1    35 f/i (1=fault)
5  owb/nea      12  crt   19  onc2
6  w-off/oobb   13  ralr

ps838 BTD

location 006164  000161301564   instruction is   btd,*ic
location 006165  006343000000   descriptor word
location 006166  006346000000   descriptor word

function in error -
 testing (ar,rl,id,reg) modification as specified by
 the (mf1),(mf2) fields using a btd instruction.
 note:  this test will fail if co's have not been
        updated to allow for ic modification.

prime results     c(y)        c(y+1)
           s/b 061062062063 066061061070
          was 061062060060 060061070060

in: 000144001000440000001762
     000144001000440000001762
dec: 180 1475 0739 7499 3906

ISOLTS claims the answer is: 

061062062063  1223
066061061070  6118
063062064061  3241
064063064070  4348
062062066060  2260
066070064067  6847
064065066067  4567
060061062063  0123
1223 6118 3241 4348 2260 6847 4567 0123
we think:
061062060060  1200
060061070060  0180
061064067065  1475
060067063071  0739
067064071071  7499
063071060066  3906
064065066067  4567
060061062063  0123
1200       0180 1475 0739 7499 3906    4567 0123
There's the value that the binary input was equal to. We must be misreading the input. Need to look at the operand descriptors carefully.

inst: 000161301564

mf1: 164  1 1 1 0100 AR, RL, ID, reg 4
mf2: 161  1 1 1 0001 AR, RL, ID, reg 1
P: 0

op1: 006343000000

process ID
iefpFinalAddress=00106343  readData=771614000014
op1 now 771614000014

Y-char91  771614
cn1 0
n1 14

op1 processes AR

DBG(20704343988)> CPU1 REGDUMPPR: PR7/sb: SNR=00000 RNR=0 WORDNO=006544 BITNO:00

771614: PR7, offset  71614. sign extend offset 771614

771614 + 006544 => address 000360

process RL: N1 is 14 is X4; X4 = 8

Our Friend Table 4-1 says that IC is only permitted in MFk.REG is C(od)32,35 if RL==0, which it not the case here. This never made sense to me; RL is concerned with the interpretation of N field of the operand, MFk.REG is concerned with that address field (Y-char).

'm convinced that the problem lies in parseNumericOperandDescriptor()'s handling of IC and MFk.RL.

That all looks right; there is something about IC that we are missing.

ps840 test-01e ill. instr. bar-100014

***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 001115   patch 001720   subtest loop point 001664

testing illegal procedure fault logic ability to
detect and trap "illegal instruction" type ipr faults.

location 001675  200000301400   instruction is   btd
location 001676  001050000004   descriptor word
location 001677  001050000004   descriptor word

prime results   ir       c(y)         fault      register
          s/b 000240 055001000001 400000000000 000000000000
          was 000240 055001000001 040000000000 000000000000
faults         s/b                       was
   illegal procedure -001675 illegal procedure - 001675

testing for ipr fault by setting bit 1
of mbz field in instruction word of btd
probable error board-

301(1) is BTD; I'm guessing this is related to ps838.

pm842 test-01c eisinterrupt bar-000776

***dsbr***  addr= 00100656 bnd= 00000 u= 1 stack= 0000
test start 100662   patch 101103   subtest loop point 101052

mlr instruction interrupt and fault priority

location 101064  000000100400   instruction is   mlr
location 101065  100700000040   descriptor word
location 101066  117020000040   descriptor word

prime results   ic     ir
          s/b 101064 000220
          was 101070 000220
mlr instruction interrupt test

DBG(9711079877)> ERR ERR: sscr set unit mode register
DBG(9711079881)> ERR ERR: sscr set unit mode register
DBG(9711079885)> ERR ERR: sscr set unit mode register

ps843 test-01a mlr- move 4 bar-100014

***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 000572   patch 000673   subtest loop point 000702

this subtest checks the mlr instruction using 4 bit
data movement. the character used is 1010.

location 000660  000100100500   instruction is   mlr
c(y+0) = 000000000000    c(y+1) = 000000000000
c(y+2) = 000000000000    c(y+3) = 000000000000
c(y+4) = 000000000000    c(y+5) = 000000000000
c(y+6) = 000000000000    c(y+7) = 000000000000

secondary results    c(y+0)       c(y+1)       c(y+2)       c(y+3)
              s/b 240000000000 000000000000 012000000000 000000000000
              was 240000000000 000000000000 000000240000 000000000000
           c(y+4)       c(y+5)       c(y+6)       c(y+7)
    s/b 000240000000 000000000000 000012000000 000000000000
    was 240000000000 000000000000 000000240000 000000000000
a 4 bit character is moved from a char position in
 a 2 word sending field to each 4 bit char in a 2
   word receiving field.  this operation is repeated
  until every char in the sending field is exercised.
data went awry during movement. check the
    data s/b vs data was printout in this err msg.

ps845 test-04a microps bar-100176

***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
unexpected illegal procedure fault at 004256 relative
calculated absolute address  104256  pr0=000000004267

***********
*** scu ***
***********

prr 0  psr 00000  p 0  fault cntr 1
trr 0  tsr 00000  cpu number 1 delta 00
tsr stat 0000  tbr 00  ic 004256  ir 000240  ca 007311
even instr- 000000024400  odd instr- 007335070010
*** apu status ***
 xsf- 0     sdwm- 0    sd-on- 1     ptwm- 0
pton- 1    pi-ap- 0    dsptw- 0    sdwnp- 0
sdwp- 0      ptw- 0     ptw2- 0      fap- 0
fanp- 1     fabs- 0
*** cu status ***
 rf- 0  rpt- 0  rd- 0  rl- 0
pot- 0  poh- 0  xde- 0  xdo- 0
poa- 0  ic- 0  rst- 0  tag- 00
*** fault data & port status ***    000000000025

ps846 test-03a a9bd test bar-100176

***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
test start 002514   patch 002603   subtest loop point 002554

this subtest is checking nine bit word,charactor,and
bit convers[on using the a9bd instruction modified
by the (q) register as a specified dr.
the results is added to the contents of the addrregister 0

location 002573  000000500506   instruction is   a9bd,ql

prime results    ar0      ar1      ar2      ar3      ar4      ar5
          s/b 00000220 25252521 25252521 25252521 25252521 00000000
          was 00000200 25252521 25252521 25252521 25252521 25252521
           ar6      ar7
    s/b 25252521 25252521
    was 25252521 25252521
secondary results   x7         a            q
              s/b 000002 000000200000 000000000010
              was 000002 000000200000 000000000010

a charactor count in the (q) register is converted
to bit string representation and added to the
contents of the address register.

probably the conversion is incorrect or the converted value
did not add correctly to the address register
the (a) register contains the contents of the
specified address register before execution.
index 7 contains the test case number.

ps847 test-01a btd test bar-100176

***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
unexpected illegal procedure fault at 000626 relative
calculated absolute address  100626  pr0=000000000024

***********
*** scu ***
***********

prr 0  psr 00000  p 0  fault cntr 1
trr 0  tsr 00000  cpu number 1 delta 00
tsr stat 0000  tbr 00  ic 000626  ir 000240  ca 000630
even instr- 000000301400  odd instr- 010701000001
*** apu status ***
 xsf- 0     sdwm- 0    sd-on- 1     ptwm- 0
pton- 1    pi-ap- 0    dsptw- 0    sdwnp- 0
sdwp- 0      ptw- 0     ptw2- 0      fap- 0
fanp- 1     fabs- 0
*** cu status ***
 rf- 0  rpt- 0  rd- 0  rl- 0
pot- 0  poh- 0  xde- 0  xdo- 0
poa- 0  ic- 0  rst- 0  tag- 00
*** fault data & port status ***    000000000025

ps848 test-01a dtb test bar-100176

***dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
unexpected illegal procedure fault at 000626 relative
calculated absolute address  100626  pr0=000000000024

***********
*** scu ***
***********

prr 0  psr 00000  p 0  fault cntr 1
trr 0  tsr 00000  cpu number 1 delta 00
tsr stat 0000  tbr 00  ic 000626  ir 000240  ca 000630
even instr- 000000305400  odd instr- 013556010002
*** apu status ***
 xsf- 0     sdwm- 0    sd-on- 1     ptwm- 0
pton- 1    pi-ap- 0    dsptw- 0    sdwnp- 0
sdwp- 0      ptw- 0     ptw2- 0      fap- 0
fanp- 1     fabs- 0
*** cu status ***
 rf- 0  rpt- 0  rd- 0  rl- 0
pot- 0  poh- 0  xde- 0  xdo- 0
poa- 0  ic- 0  rst- 0  tag- 00
*** fault data & port status ***    000000000025

ps849 test-02a overfl test bar-100176

**dsbr***  addr= 00017042 bnd= 00000 u= 1 stack= 0000
unexpected illegal procedure fault at 000736 relative
calculated absolute address  100736  pr0=000000000677

***********
*** scu ***
***********

prr 0  psr 00000  p 0  fault cntr 1
trr 0  tsr 00000  cpu number 1 delta 00
tsr stat 0000  tbr 00  ic 000736  ir 000240  ca 000740
even instr- 000000301400  odd instr- 003077000001
*** apu status ***
 xsf- 0     sdwm- 0    sd-on- 1     ptwm- 0
pton- 1    pi-ap- 0    dsptw- 0    sdwnp- 0
sdwp- 0      ptw- 0     ptw2- 0      fap- 0
fanp- 1     fabs- 0
*** cu status ***
 rf- 0  rpt- 0  rd- 0  rl- 0
pot- 0  poh- 0  xde- 0  xdo- 0
poa- 0  ic- 0  rst- 0  tag- 00
*** fault data & port status ***    000000000025

pa860 test-02a des/seg-npge bar-100176

test start 102250   patch 102420   subtest loop point 102314

des segment & segment -- non paged

location 102330  025252212310   instruction is   absa,0

prime results    ar0    snr0 rnr0   x0         a
          s/b 00000000 00000  0   000000 000252520000
          was 00000000 00000  0   000000 000252520000
secondary results   x1     x2     x3     x4     x5     x6     x7
              s/b 000001 000002 000003 000004 000005 000006 000007
              was 000001 000002 000003 000004 000005 000006 000007
              q       e
    s/b 000000000000 000
    was 000000000000 000

executing absa inst in absolute with bit 29 on
with "r" and "adr" modifications
contents of associative memory - sdw in error

***********
*** sdw ***
***********

address  r1 r2 r3 f fc bound r e w p u g x  cl
00000000 0  0  0  1 0  37777 1 1 1 1 1 1 0 00000

-------------------------sdw associative memory-------------------------
level a
  seg-pntr  f    lru   sdw-addr  r1  r2  r3  seg-bnd  rewpugc   cl   par

[00] 00000  0  000000  00200000   0   0   0   37777   1111110  00000  0
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