Design for a 32/64 bit version of the DPS8M architecture to be implemented as a virtual machine.
This architecture is intented to facilitate the porting the Multics source code to a modern hardware platform. To this end, the design has the following goals:
- Resemble the DPS8M hardware enough that porting is feasible.
- Be a transition design enabling the implementation of a dervied design in hardware.
- Be a platform for experimenting with architecural changes to support Multics evolution.
Support the DPS8M memory model
- Ring brackets
- Ring Alarm
Support the DPS8M indirection model to allow
- Directed Faults
- Linkage Offset Table
The instruction set should otherwise be as close to the host architecture (nominally x86 or x86_64) as is convenient,
so as to allow an efficient virtual machine implementation.
- Integer and floating point data types in host format.
Tentative proposed architecture:
- 64 bit general registers
- 48 bit virtual address space
- 48 bit physical address space
- 8 bit byte addressable memory
- page size TBD
- A, Q registers: 64 bit
- E register: 15 bit (compatible with IEEE 754 binary128 format)
- Index registers: 16 * 48-bit index registers
- Indicator register (Zero, Negative, Carry, Overflow, Exponent overflow, Exponent underflow, Overflow mask, Tally runout, Truncation, Mid instruction interrupt/fault, Absolute mode)
- Timer register: to be determined.
- Ring alarm register: to be determined.
- Pointer registers: 16 x
- Word number: 48 bits
- Segment number: 16 bits
- Ring number 6 bits
- Bit number: to be determined
- Tag: to be determined.
- Procedure Pointer Register (PPR)
- Procedure Ring Register (PRR): 6 bits
- Procedure Segment Register (PSR): 16 bits
- Instruction Counter (IC): 48 bits
- Temporary Pointer Register (TPR)
- Temporary Ring Register (TRR): 6 bits
- Temporary Segment Register (TSR): 16 bits:
- Computed Address (CA): 48 bits
- Descriptor Segment Base Register (DSBR)
- Address (ADDR): 48 bits
- Bound (BND): TBD
- U: 1 bit
- STACK: TBD
- Segment Descriptor Word (SDW):
- ADDR: 48 bits
- R1: 6 bits
- R2: 6 bits
- R3: 6 bits
- BOUND: TBD
- R: 1 bit
- E: 1 bit
- W: 1 bit
- P: 1 bit
- U: 1 bit
- G: 1 bit
- C: 1 bit, TBD
- CL: TBD
- POINTER: 16 bits
- Page Table Word (PTW)
- ADDR: TBD (48 bits less log2 of the page size)
- M: 1 bit
- POINTER: 48 bits
- PAGENO: TBD (48 bits less log2 of the page size)
- Fault Register: TBD
- Mode Register: TBD
- Cache Mode Register (CMR): TBD
- Control Unit Data: TBD
- History registers: TBD
DPS8M-64 Manual: [http://ringzero.wikidot.com/wiki:dps8m-32-manual]