CAC 2021-12-08
MCS code crashes 25 instructions in
DBG(246435)> CPU TRACE: 55505:450134 STX3 134,I
55505 init:04427
04427 4 50 134 4563 1971 stx3 a.t017-*,* (intcel) set interrupt cell
DBG(246435)> CPU CAF: CAF entry: I 1 T 0 D 134
DBG(246435)> CPU CAF: word addressing; wt 55641
DBG(246435)> CPU CAF: indirect cycle start Y 55641 ct 0 CY 055461 t 0
DBG(246435)> CPU CAF: CAF Exit C 0 W 55461
DBG(246435)> CPU REG: rX3 RD 033400
DBG(246435)> CPU FINAL: Write Addr: 55461 Data: 033400
DBG(246436)> CPU TRACE: 55506:333100 INH
55506 init:04430
04430 3331 00 0 1973 inh inhibit interrupts <-><-><-><-><-><-><-><-><-><
DBG(246437)> CPU TRACE: 55507:417121 STA 121,I
55507 init:04431
04431 4 17 121 4552 1975 sta a.t003-*,* (diachn) save dia i/o channel
DBG(246437)> CPU CAF: CAF entry: I 1 T 0 D 121
DBG(246437)> CPU CAF: word addressing; wt 55630
DBG(246437)> CPU CAF: indirect cycle start Y 55630 ct 0 CY 053157 t 0
DBG(246437)> CPU CAF: CAF Exit C 0 W 53157
DBG(246437)> CPU REG: rA RD 000004
DBG(246437)> CPU FINAL: Write Addr: 53157 Data: 000004
DBG(246438)> CPU TRACE: 55510:033604 ALS
55510 init:04432
04432 0336 04 0 1977 als 4 which is 16*(channel)+2
DBG(246438)> CPU REG: rA RD 000004
DBG(246438)> CPU REG: rIR WR 064004 zncOIpVe Channel 04
DBG(246438)> CPU REG: rA RD 000004
DBG(246438)> CPU REG: rA WR 000010
DBG(246438)> CPU REG: rA RD 000010
DBG(246438)> CPU REG: rA WR 000020
DBG(246438)> CPU REG: rA RD 000020
DBG(246438)> CPU REG: rA WR 000040
DBG(246438)> CPU REG: rA RD 000040
DBG(246438)> CPU REG: rA WR 000100
DBG(246438)> CPU REG: rIR WR 064004 zncOIpVe Channel 04
DBG(246439)> CPU TRACE: 55511:773002 IAA
55511 init:04433
04433 773 002 0 1978 iaa 2
DBG(246439)> CPU REG: rA RD 000100
DBG(246439)> CPU REG: rA WR 000102
DBG(246439)> CPU REG: rIR WR 064004 zncOIpVe Channel 04
DBG(246440)> CPU TRACE: 55512:417124 STA 124,I
55512 init:04434
04434 4 17 124 4560 1979 sta a.t010-*,* diatmv
DBG(246440)> CPU CAF: CAF entry: I 1 T 0 D 124
DBG(246440)> CPU CAF: word addressing; wt 55636
DBG(246440)> CPU CAF: indirect cycle start Y 55636 ct 0 CY 053160 t 0
DBG(246440)> CPU CAF: CAF Exit C 0 W 53160
DBG(246440)> CPU REG: rA RD 000102
DBG(246440)> CPU FINAL: Write Addr: 53160 Data: 000102
DBG(246441)> CPU TRACE: 55513:407121 LDA 121,I
55513 init:04435
04435 4 07 121 4556 1985 lda a.t008-*,* (.crmem) get memory size
DBG(246441)> CPU CAF: CAF entry: I 1 T 0 D 121
DBG(246441)> CPU CAF: word addressing; wt 55634
DBG(246441)> CPU CAF: indirect cycle start Y 55634 ct 0 CY 000651 t 0
DBG(246441)> CPU CAF: CAF Exit C 0 W 00651
DBG(246441)> CPU FINAL: Read Addr: 00651 Data: 177777
DBG(246441)> CPU REG: rA WR 177777
DBG(246441)> CPU REG: rIR WR 064004 zncOIpVe Channel 04
DBG(246442)> CPU TRACE: 55514:417117 STA 117,I
55514 init:04436
04436 4 17 117 4555 1986 sta a.t007-*,* (mvplmm) set lower memory maximum address
DBG(246442)> CPU CAF: CAF entry: I 1 T 0 D 117
DBG(246442)> CPU CAF: word addressing; wt 55633
DBG(246442)> CPU CAF: indirect cycle start Y 55633 ct 0 CY 046446 t 0
DBG(246442)> CPU CAF: CAF Exit C 0 W 46446
DBG(246442)> CPU REG: rA RD 177777
DBG(246442)> CPU FINAL: Write Addr: 46446 Data: 177777
DBG(246443)> CPU TRACE: 55515:017145 STA 145
55515 init:04437
04437 0 17 145 4604 1987 sta istpcl-* stops memory clear loop
DBG(246443)> CPU CAF: CAF entry: I 0 T 0 D 145
DBG(246443)> CPU CAF: word addressing; wt 55662
DBG(246443)> CPU CAF: CAF Exit C 0 W 55662
DBG(246443)> CPU REG: rA RD 177777
DBG(246443)> CPU FINAL: Write Addr: 55662 Data: 177777
DBG(246444)> CPU TRACE: 55516:027131 CMPA 131
55516 init:04440
04440 0 27 131 4571 1988 cmpa l.t002-* (=32768) is last address above 32k?
DBG(246444)> CPU CAF: CAF entry: I 0 T 0 D 131
DBG(246444)> CPU CAF: word addressing; wt 55647
DBG(246444)> CPU CAF: CAF Exit C 0 W 55647
DBG(246444)> CPU FINAL: Read Addr: 55647 Data: 100000
DBG(246444)> CPU REG: rA RD 177777
DBG(246444)> CPU REG: rIR WR 164004 znCOIpVe Channel 04
DBG(246445)> CPU TRACE: 55517:445126 TNC 126,I
55517 init:04441
04441 4 45 126 4567 1989 tnc a.t022-*,* (stop06) no. we can't run this code
DBG(246445)> CPU CAF: CAF entry: I 1 T 0 D 126
DBG(246445)> CPU CAF: word addressing; wt 55645
DBG(246445)> CPU CAF: indirect cycle start Y 55645 ct 0 CY 054362 t 0
DBG(246445)> CPU CAF: CAF Exit C 0 W 54362
DBG(246445)> CPU REG: rIR RD 164004 znCOIpVe Channel 04
DBG(246446)> CPU TRACE: 55520:007127 LDA 127
55520 init:04442
04442 0 07 127 4571 1990 lda l.t002-* (=32768) yes. calculate last address in lower 32k
DBG(246446)> CPU CAF: CAF entry: I 0 T 0 D 127
DBG(246446)> CPU CAF: word addressing; wt 55647
DBG(246446)> CPU CAF: CAF Exit C 0 W 55647
DBG(246446)> CPU FINAL: Read Addr: 55647 Data: 100000
DBG(246446)> CPU REG: rA WR 100000
DBG(246446)> CPU REG: rIR WR 164004 znCOIpVe Channel 04
DBG(246447)> CPU TRACE: 55521:773777 IAA
55521 init:04443
04443 773 777 0 1991 iaa -1
DBG(246447)> CPU REG: rA RD 100000
DBG(246447)> CPU REG: rA WR 077777
DBG(246447)> CPU REG: rIR WR 164004 znCOIpVe Channel 04
DBG(246448)> CPU TRACE: 55522:017140 STA 140
55522 init:04444
04444 0 17 140 4604 1992 sta istpcl-* stops memory clear loop
DBG(246448)> CPU CAF: CAF entry: I 0 T 0 D 140
DBG(246448)> CPU CAF: word addressing; wt 55662
DBG(246448)> CPU CAF: CAF Exit C 0 W 55662
DBG(246448)> CPU REG: rA RD 077777
DBG(246448)> CPU FINAL: Write Addr: 55662 Data: 077777
DBG(246449)> CPU TRACE: 55523:773400 IAA
55523 init:04445
04445 773 400 0 1993 iaa -256 account for paging window
DBG(246449)> CPU REG: rA RD 077777
DBG(246449)> CPU REG: rA WR 077377
DBG(246449)> CPU REG: rIR WR 164004 znCOIpVe Channel 04
DBG(246450)> CPU TRACE: 55524:773400 IAA
55524 init:04446
04446 773 400 0 1994 iaa -256 and buffer window
DBG(246450)> CPU REG: rA RD 077377
DBG(246450)> CPU REG: rA WR 076777
DBG(246450)> CPU REG: rIR WR 164004 znCOIpVe Channel 04
DBG(246451)> CPU TRACE: 55525:417106 STA 106,I
55525 init:04447
04447 4 17 106 4555 1995 sta a.t007-*,* (mvplmm) set lower memory maximum address
DBG(246451)> CPU CAF: CAF entry: I 1 T 0 D 106
DBG(246451)> CPU CAF: word addressing; wt 55633
DBG(246451)> CPU CAF: indirect cycle start Y 55633 ct 0 CY 046446 t 0
DBG(246451)> CPU CAF: CAF Exit C 0 W 46446
DBG(246451)> CPU REG: rA RD 076777
DBG(246451)> CPU FINAL: Write Addr: 46446 Data: 076777
DBG(246452)> CPU TRACE: 55526:043130 LDX1 130
55526 init:04450
04450 0 43 130 4600 1999 ldx1 l.t009-* get address of loc. 0
DBG(246452)> CPU CAF: CAF entry: I 0 T 0 D 130
DBG(246452)> CPU CAF: word addressing; wt 55656
DBG(246452)> CPU CAF: CAF Exit C 0 W 55656
DBG(246452)> CPU FINAL: Read Addr: 55656 Data: 000000
DBG(246452)> CPU REG: rX1 WR 000000
DBG(246452)> CPU REG: rIR WR 564004 ZnCOIpVe Channel 04
DBG(246453)> CPU TRACE: 55527:107000 LDA 0,1
55527 init:04451
04451 1 07 000 0 2000 lda 0,1 save its contents
DBG(246453)> CPU CAF: CAF entry: I 0 T 1 D 000
DBG(246453)> CPU CAF: after getT ct 0 wt 00000
DBG(246453)> CPU CAF: w6 00000
DBG(246453)> CPU CAF: CAF Exit (I && CT) C 0 W 00000
DBG(246453)> CPU FINAL: Read Addr: 00000 Data: 000000
DBG(246453)> CPU REG: rA WR 000000
DBG(246453)> CPU REG: rIR WR 564004 ZnCOIpVe Channel 04
DBG(246454)> CPU TRACE: 55530:017135 STA 135
55530 init:04452
04452 0 17 135 4607 2001 sta itloc0-*
DBG(246454)> CPU CAF: CAF entry: I 0 T 0 D 135
DBG(246454)> CPU CAF: word addressing; wt 55665
DBG(246454)> CPU CAF: CAF Exit C 0 W 55665
DBG(246454)> CPU REG: rA RD 000000
DBG(246454)> CPU FINAL: Write Addr: 55665 Data: 000000
DBG(246455)> CPU TRACE: 55531:673777 QRL
55531 init:04453
04453 673 777 0 2002 ila -1 put something recognizable there
DBG(246455)> CPU REG: rA WR 777777
DBG(246455)> CPU REG: rIR WR 364004 zNCOIpVe Channel 04
DBG(246456)> CPU TRACE: 55532:117000 STA 0,1
55532 init:04454
04454 1 17 000 0 2003 sta 0,1
DBG(246456)> CPU CAF: CAF entry: I 0 T 1 D 000
DBG(246456)> CPU CAF: after getT ct 0 wt 00000
DBG(246456)> CPU CAF: w6 00000
DBG(246456)> CPU CAF: CAF Exit (I && CT) C 0 W 00000
DBG(246456)> CPU REG: rA RD 777777
DBG(246456)> CPU FINAL: Write Addr: 00000 Data: 777777
DBG(246457)> CPU TRACE: 55533:043116 LDX1 116
55533 init:04455
04455 0 43 116 4573 2004 ldx1 l.t004-* (window) base of window
DBG(246457)> CPU CAF: CAF entry: I 0 T 0 D 116
DBG(246457)> CPU CAF: word addressing; wt 55651
DBG(246457)> CPU CAF: CAF Exit C 0 W 55651
DBG(246457)> CPU FINAL: Read Addr: 55651 Data: 077400
DBG(246457)> CPU REG: rX1 WR 077400
DBG(246457)> CPU REG: rIR WR 364004 zNCOIpVe Channel 04
DBG(246458)> CPU TRACE: 55534:156000 STZ 0,1
55534 init:04456
04456 1 56 000 0 2005 stz 0,1 clear test cells
DBG(246458)> CPU CAF: CAF entry: I 0 T 1 D 000
DBG(246458)> CPU CAF: after getT ct 0 wt 77400
DBG(246458)> CPU CAF: w6 00000
DBG(246458)> CPU CAF: CAF Exit (I && CT) C 0 W 77400
DBG(246458)> CPU FINAL: Write Addr: 77400 Data: 000000
DBG(246459)> CPU TRACE: 55535:156400 STZ 400,1
55535 init:04457
04457 1 56 400 0 2006 stz -256,1
DBG(246459)> CPU CAF: CAF entry: I 0 T 1 D 400
DBG(246459)> CPU CAF: after getT ct 0 wt 77400
DBG(246459)> CPU CAF: w6 00000
fault 00445 : addAddr32(): illegal charAddr
simCycles = 246459
Unknown error, IC: 55535
Goodbye
1961 *********************************************
1962 * gicb enters inti by way of
1963 * tra =(istart-1),*
1964 *
1965 * and passes:
1966 * the highest address in mcs in x2
1967 * the interrupt cell for the cs in x3
1968 * the dia iom channel in the a
1969 **********************************************
1970
04427 4 50 134 4563 1971 stx3 a.t017-*,* (intcel) set interrupt cell
04430 1972 istart null
04430 3331 00 0 1973 inh inhibit interrupts <-><-><-><-><-><-><-><-><-><
1974
04431 4 17 121 4552 1975 sta a.t003-*,* (diachn) save dia i/o channel
1976 and derive terminate interrupt vector address
04432 0336 04 0 1977 als 4 which is 16*(channel)+2
04433 773 002 0 1978 iaa 2
04434 4 17 124 4560 1979 sta a.t010-*,* diatmv
1980
1981 **************************************************************
1982 * clear all unused configured memory including extended memory
1983 **************************************************************
1984
04435 4 07 121 4556 1985 lda a.t008-*,* (.crmem) get memory size
04436 4 17 117 4555 1986 sta a.t007-*,* (mvplmm) set lower memory maximum address
04437 0 17 145 4604 1987 sta istpcl-* stops memory clear loop
04440 0 27 131 4571 1988 cmpa l.t002-* (=32768) is last address above 32k?
04441 4 45 126 4567 1989 tnc a.t022-*,* (stop06) no. we can't run this code
04442 0 07 127 4571 1990 lda l.t002-* (=32768) yes. calculate last address in lower 32k
04443 773 777 0 1991 iaa -1
04444 0 17 140 4604 1992 sta istpcl-* stops memory clear loop
04445 773 400 0 1993 iaa -256 account for paging window
04446 773 400 0 1994 iaa -256 and buffer window
04447 4 17 106 4555 1995 sta a.t007-*,* (mvplmm) set lower memory maximum address
1996 *
1997 * check pager operation
1998 *
04450 0 43 130 4600 1999 ldx1 l.t009-* get address of loc. 0
04451 1 07 000 0 2000 lda 0,1 save its contents
04452 0 17 135 4607 2001 sta itloc0-*
04453 673 777 0 2002 ila -1 put something recognizable there
04454 1 17 000 0 2003 sta 0,1
04455 0 43 116 4573 2004 ldx1 l.t004-* (window) base of window
04456 1 56 000 0 2005 stz 0,1 clear test cells
04457 1 56 400 0 2006 stz -256,1
Fixed Multics to think that the FNP is a 32K DN355.
04435 4 07 121 4556 1985 lda a.t008-*,* (.crmem) get memory size
04436 4 17 117 4555 1986 sta a.t007-*,* (mvplmm) set lower memory maximum address
04437 0 17 145 4604 1987 sta istpcl-* stops memory clear loop
04440 0 27 131 4571 1988 cmpa l.t002-* (=32768) is last address above 32k?
04441 4 45 126 4567 1989 tnc a.t022-*,* (stop06) no. we can't run this code
[[code]]
DBG(246703)> CPU TRACE: 55313:407121 LDA 121,I
55313 init:04435
04435 4 07 121 4556 1985 lda a.t008-*,* (.crmem) get memory size
DBG(246703)> CPU CAF: CAF entry: I 1 T 0 D 121
DBG(246703)> CPU CAF: word addressing; wt 55434
DBG(246703)> CPU CAF: indirect cycle start Y 55434 ct 0 CY 000651 t 0
DBG(246703)> CPU CAF: CAF Exit C 0 W 00651
DBG(246703)> CPU FINAL: Read Addr: 00651 Data: 077777
DBG(246703)> CPU REG: rA WR 077777
DBG(246703)> CPU REG: rIR WR 064004 zncOIpVe Channel 04
DBG(246706)> CPU TRACE: 55316:027131 CMPA 131
55316 init:04440
04440 0 27 131 4571 1988 cmpa l.t002-* (=32768) is last address above 32k?
DBG(246706)> CPU CAF: CAF entry: I 0 T 0 D 131
DBG(246706)> CPU CAF: word addressing; wt 55447
DBG(246706)> CPU CAF: CAF Exit C 0 W 55447
DBG(246706)> CPU FINAL: Read Addr: 55447 Data: 100000
DBG(246706)> CPU REG: rA RD 077777
DBG(246706)> CPU REG: rIR WR 264004 zNcOIpVe Channel 04
[DBG(246707)> CPU TRACE: 55317:445126 TNC 126,I
55317 init:04441
04441 4 45 126 4567 1989 tnc a.t022-*,* (stop06) no. we can't run this code
DBG(246707)> CPU CAF: CAF entry: I 1 T 0 D 126
DBG(246707)> CPU CAF: word addressing; wt 55445
DBG(246707)> CPU CAF: indirect cycle start Y 55445 ct 0 CY 054162 t 0
DBG(246707)> CPU CAF: CAF Exit C 0 W 54162
DBG(246707)> CPU REG: rIR RD 264004 zNcOIpVe Channel 04
[/code]]
A 077777
Y 100000
dd01 pg 88, 89
Unsigned compare
A < Y Z 0, C 0
So it is working as documented.
page revision: 1, last edited: 08 Dec 2021 21:29
