CAC 2021-12-07
FNP checksum
DBG(288012)> CPU SRC: 00506 0 24 266 774 269 sbaq icksma-* compare cksum to that made by cs system
DBG(288012)> CPU FINAL: Read Addr: 00774 Data: 734410
DBG(288012)> CPU FINAL: Read Addr: 00775 Data: 560716
DBG(288012)> CPU REG: rA RD 745511
DBG(288012)> CPU REG: rQ RD 055113
734410560716
745511055113
251 compute checksum
252
00466 0 07 305 773 253 lda iclmts+1-* calculate length of mcs
00467 0 26 303 772 254 sba iclmts-* *
00470 4332 00 255 cax1 move to index one
00471 0 44 161 652 256 ldi icindc-* reset indicator storage
00472 0 54 760 452 257 sti diaind-* *
00473 0 71 005 500 258 tra 5 branch around zeroes
259
00474 000000 260 dec 0 two words of zeroes that must be at loc
00475 000000 261 dec 0 474 & 475 so that pager won't be activated
00476 000000 262 dec 0 476-477 is dn6670 'yellow' counter and is
00477 000000 263 dec 0 incremented by one for each edac error
264
00500 0 03 166 666 265 ldx2 lmcs2-* get starting location plus two
00501 0 04 277 1000 266 ldaq .mcs.-* get first two words
00502 173 776 267 iacx1 -2 reduce length
00503 268 cksum calculate checksum for mcs/fnp
00503 0 41 002 505 ldx3 2
00504 0 71 057 563 tra cksum-*
00505 0 00505 ind *
00506 0 24 266 774 269 sbaq icksma-* compare cksum to that made by cs system
00507 0 64 026 535 270 tnz icgtcr-* ***checksum error***
TRACE: 00466:007305 LDA 305
SRC: 00466 0 07 305 773 253 lda iclmts+1-* calculate length of mcs
FINAL: Read Addr: 00773 Data: 056410
REG: rA WR 056410
TRACE: 00467:026303 SBA 303
SRC: 00467 0 26 303 772 254 sba iclmts-* *
FINAL: Read Addr: 00772 Data: 000000
REG: rA RD 056410
REG: rA WR 056410
TRACE: 00470:433200 CAX1
SRC: 00470 4332 00 255 cax1 move to index one
REG: rA RD 056410
REG: rX1 WR 056410
TRACE: 00471:044161 LDI 161
SRC: 00471 0 44 161 652 256 ldi icindc-* reset indicator storage
FINAL: Read Addr: 00652 Data: 024004
REG: rIR WR 024004 zncoIpVe Channel 04
TRACE: 00472:054760 STI 760
SRC: 00472 0 54 760 452 257 sti diaind-* *
REG: rIR RD 024004 zncoIpVe Channel 04
FINAL: Write Addr: 00452 Data: 024004
TRACE: 00473:071005 TRA 5
SRC: 00473 0 71 005 500 258 tra 5 branch around zeroes
TRACE: 00500:003166 LDX2 166
SRC: 00500 0 03 166 666 265 ldx2 lmcs2-* get starting location plus two
FINAL: Read Addr: 00666 Data: 001002
REG: rX2 WR 001002
REG: rIR WR 024004 zncoIpVe Channel 04
TRACE: 00501:004277 LDAQ 277
SRC: 00501 0 04 277 1000 266 ldaq .mcs.-* get first two words
FINAL: Read Addr: 01000 Data: 000000
FINAL: Read Addr: 01001 Data: 000000
REG: rA WR 000000
REG: rQ WR 000000
REG: rIR WR 424004 ZncoIpVe Channel 04
TRACE: 00502:173776 IACX1
SRC: 00502 173 776 267 iacx1 -2 reduce length
REG: rX1 RD 056410
REG: rX1 WR 056406
REG: rIR WR 024004 zncoIpVe Channel 04
TRACE: 00503:041002 LDX3 2
SRC: 00503 0 41 002 505 ldx3 2
FINAL: Read Addr: 00505 Data: 000505
REG: rX3 WR 000505
REG: rIR WR 024004 zncoIpVe Channel 04
TRACE: 00504:071057 TRA 57
SRC: 00504 0 71 057 563 tra cksum-*
00563 330 cksum null
00563 0 44 667 452 331 ldi diaind-* get the indicators
00564 0 45 002 566 332 tnc 2 test for carry
00565 0 15 063 650 333 adaq diary-* carry. simulate awc instruction
00566 2 15 000 334 adaq 0,2 add in next word
00567 0 54 663 452 335 sti diaind-* save indicators
00570 273 002 336 iacx2 2 bump data pointer
00571 173 776 337 iacx1 -2 reduce counter
00572 0 64 771 563 338 tnz cksum-* continue to end of block
00573 3 71 001 339 tra 1,3 return
340
First tile through the loop:
: 00563:044667 LDI 667
SRC: 00563 0 44 667 452 331 ldi diaind-* get the indicators
FINAL: Read Addr: 00452 Data: 024004
REG: rIR WR 024004 zncoIpVe Channel 04
TRACE: 00564:045002 TNC 2
SRC: 00564 0 45 002 566 332 tnc 2 test for carry
REG: rIR RD 024004 zncoIpVe Channel 04
TRACE: 00566:215000 ADAQ 0,2
SRC: 00566 2 15 000 334 adaq 0,2 add in next word
FINAL: Read Addr: 01002 Data: 000000
FINAL: Read Addr: 01003 Data: 000000
REG: rA RD 000000
REG: rQ RD 000000
TRACE: ADAQ 000000000000
TRACE: ADAQ + 000000000000
TRACE: ADAQ = 0000000000000
REG: rA WR 000000
REG: rQ WR 000000
REG: rIR WR 424004 ZncoIpVe Channel 04
TRACE: 00567:054663 STI 663
SRC: 00567 0 54 663 452 335 sti diaind-* save indicators
REG: rIR RD 424004 ZncoIpVe Channel 04
FINAL: Write Addr: 00452 Data: 424004
TRACE: 00570:273002 IACX2
SRC: 00570 273 002 336 iacx2 2 bump data pointer
REG: rX2 RD 001002
REG: rX2 WR 001004
REG: rIR WR 024004 zncoIpVe Channel 04
TRACE: 00571:173776 IACX1
SRC: 00571 173 776 337 iacx1 -2 reduce counter
REG: rX1 RD 056406
REG: rX1 WR 056404
REG: rIR WR 024004 zncoIpVe Channel 04
TRACE: 00572:064771 TNZ 771
SRC: 00572 0 64 771 563 338 tnz cksum-* continue to end of block
REG: rIR RD 024004 zncoIpVe Channel 04
Second trip:
[[code]]
TRACE: 00566:215000 ADAQ 0,2
SRC: 00566 2 15 000 334 adaq 0,2 add in next word
FINAL: Read Addr: 01004 Data: 000000
FINAL: Read Addr: 01005 Data: 000000
REG: rA RD 000000
REG: rQ RD 000000
TRACE: ADAQ 000000000000
TRACE: ADAQ + 000000000000
TRACE: ADAQ = 0000000000000
REG: rA WR 000000
REG: rQ WR 000000
REG: rIR WR 424004 ZncoIpVe Channel 04
[[/code]]
Hmm. Zeros, they work.
[[code]]
ds >system_library_unbundled>site_mcs 0 10000
000000 000000027204 000000000000 000000000000 000000000000
000004 000000000000 000000000000 000000000000 000000000000
======
000320 000000000000 000000147031 743322613240 000000000000
000324 000000000000 000000177777 000000004200 000003000000
000330 000000004562 000000317777 000000000000 000000000000
000334 000000000000 067056066143 000000000000 000000000000
000340 000000000000 000000004000 004177004000 000000000000
000344 000000000000 004176000000 000000000000 000000000000
000350 000000000000 000000000000 000000000000 000000000000
[[/code]]
Skipping ahead...
NB. Addressing: The core image starting at offset 1 has been copied to a buffer in the dn355 starting at 01000.
Memory is 18 bit, so divide by 2 to get the dps8m offset:
[[code]]
(01640 - 01000) / 2 + 1--> 321
[[/code]]
[[code]]
TRACE: 00566:215000 ADAQ 0,2
SRC: 00566 2 15 000 334 adaq 0,2 add in next word
FINAL: Read Addr: 01640 Data: 000000
FINAL: Read Addr: 01641 Data: 147031
REG: rA RD 000000
REG: rQ RD 000000
TRACE: ADAQ 000000000000
TRACE: ADAQ + 000000147031
TRACE: ADAQ = 0000000147031
REG: rA WR 000000
REG: rQ WR 147031
REG: rIR WR 024004 zncoIpVe Channel 04
[[/code]]
[[code]]
TRACE: 00566:215000 ADAQ 0,2
SRC: 00566 2 15 000 334 adaq 0,2 add in next word
FINAL: Read Addr: 01642 Data: 743322
FINAL: Read Addr: 01643 Data: 613240
REG: rA RD 000000
REG: rQ RD 147031
TRACE: ADAQ 000000147031
TRACE: ADAQ + 743322613240
TRACE: ADAQ = 0743322762271
REG: rA WR 743322
REG: rQ WR 762271
REG: rIR WR 224004 zNcoIpVe Channel 04
[[/code]]
Looks good.
load_fnp_ does all kinds of patching to the core image; I don't know where, so differences between the data in the ds and in the buffer are most likely due to that pathing.
Looking for an overflow case:
[[code]]
TRACE: 00566:215000 ADAQ 0,2
SRC: 00566 2 15 000 334 adaq 0,2 add in next word
FINAL: Read Addr: 01646 Data: 073553
FINAL: Read Addr: 01647 Data: 646522
REG: rA RD 743323
REG: rQ RD 136647
TRACE: ADAQ 743323136647
TRACE: ADAQ + 073553646522
TRACE: ADAQ = 1037077005371
REG: rA WR 037077
REG: rQ WR 005371
REG: rIR WR 124004 znCoIpVe Channel 04
[[/code]]
Looks correct...
Something odd is going on at the end of the data, tho. The last non-zero ADAQ:
[[code]]
FINAL: Read Addr: 20776 Data: 422016
FINAL: Read Addr: 20777 Data: 075002
TRACE: ADAQ 323472760111
TRACE: ADAQ + 422016075002
TRACE: ADAQ = 0745511055113
[[/code]]
and next:
[[code]]
FINAL: Read Addr: 21000 Data: 000000
FINAL: Read Addr: 21001 Data: 000000
TRACE: ADAQ 745511055113
TRACE: ADAQ + 000000000000
TRACE: ADAQ = 0745511055113
[[/code]]
Looking at site_mcs:
[[code]]
007774 410003010001 020010050472 000000407020 075004074014
010000 422016075002 111004422010 474012422013 065004004023
[[/code]]
Addresses 20776 and 7 had correct data: 010000:422016075002, but 21000 and 1 have zeros instead of 111004422010.
The remaining buffer memory (21000-57407) is filled with zeros.
[[code]]
$ grep < dn355.debug -w DMA | grep 00001004
DBG: DMA 00010602 000000000000 00001004
DBG: DMA 00010602 000000000000 00001004
DBG: DMA 00010602 000000000000 00001004
The buffer is getting written to 3 times. There are more words to transfer then can be handled by an DCW; the maximum tally is 4096, to multiple DCWs are used. I suspect that the addresses are getting reset and
each DCW is transferring the same data.
No; each transfer has its own CIOC, so something i wrong in the way that gicb is setting up the xfers…
page revision: 3, last edited: 07 Dec 2021 18:54