CAC 2017-04-26

ISOLTS 880 05a

DBG(4791151150)> CPU TRACE: 1: 105274 100000610300 (RTCD PR1|0) 000000 610(0) 1 1 0 00
DBG(4791151150)> CPU APPENDING: doPtrReg(): PR[1] SNR=00000 RNR=0 WORDNO=106204 BITNO=00
DBG(4791151150)> CPU APPENDING: doPtrReg(): n=1 offset=00000 TPR.CA=106204 TPR.TBR=0 TPR.TSR=00000 TPR.TRR=0
DBG(4791151150)> CPU APPENDING: doAppendCycle(Entry) thisCycle=RTCD_OPERAND_FETCH
DBG(4791151150)> CPU APPENDING: doAppendCycle(Entry) lastCycle=INSTRUCTION_FETCH
DBG(4791151150)> CPU APPENDING: doAppendCycle(Entry) CA 106204
DBG(4791151150)> CPU APPENDING: doAppendCycle(Entry) n= 2
DBG(4791151150)> CPU APPENDING: doAppendCycle(Entry) PPR.PRR=0 PPR.PSR=00000
DBG(4791151150)> CPU APPENDING: doAppendCycle(Entry) TPR.TRR=0 TPR.TSR=00000
DBG(4791151150)> CPU APPENDING: doAppendCycle(Entry) isb29 PRNO 1
DBG(4791151150)> CPU APPENDING: doAppendCycle(Entry) XSF 0
DBG(4791151150)> CPU CAC: RNR 0 PRR 0
DBG(4791151150)> CPU CAC: TRR set to PRR 0
DBG(4791151150)> CPU APPENDING: TSN TSR 00000 TRR 0
DBG(4791151150)> CPU APPENDING: doAppendCycle(A)
DBG(4791151150)> CPU APPENDING: fetchNSDW(0):segno=00000
DBG(4791151150)> CPU APPENDING: fetchNSDW(2):fetching SDW from 100736
DBG(4791151150)> CPU CORE: core_read2 20100736 000000000774 (fetchNSDW)
DBG(4791151150)> CPU CORE: core_read2 20100737 377777700000 (fetchNSDW)
DBG(4791151150)> CPU APPENDING: fetchNSDW(2):SDW0=ADDR=000000 R1=0 R2=7 R3=7 F=1 FC=0 BOUND=37777 R=1 E=1 W=1 P=1 U=1 G=1 C=0 EB=0
DBG(4791151150)> CPU APPENDING: doAppendCycle(A) R1 0 R2 7 R3 7 E 1
DBG(4791151150)> CPU APPENDING: doAppendCycle(B)
DBG(4791151150)> CPU APPENDING: doAppendCycle(B):!STR-OP
DBG(4791151150)> CPU APPENDING: doAppendCycle(G)
DBG(4791151150)> CPU APPENDING: doAppendCycle(H): FANP
DBG(4791151150)> CPU APPENDING: doAppendCycle(H): SDW->ADDR=00000000 CA=106204
DBG(4791151150)> CPU APPENDING: doAppendCycle(H:FANP): (00000:106204) finalAddress=00106204
DBG(4791151150)> CPU APPENDING: doAppendCycle(HI)
DBG(4791151150)> CPU CORE: core_read  20106204 000000100000 (RTCD_OPERAND_FETCH)
DBG(4791151150)> CPU CORE: core_read  20106205 106242000000 (RTCD_OPERAND_FETCH)
DBG(4791151150)> CPU APPENDING: doAppendCycle(K)
DBG(4791151150)> CPU CAC: [4791151150] Y18,20 1 TRR 0 R1 0 PRR 0
DBG(4791151150)> CPU APPENDING: doAppendCycle(KL)
DBG(4791151150)> CPU APPENDING: doAppendCycle(M)
DBG(4791151150)> CPU APPENDING: doAppendCycle (Exit) PRR 1 PSR 00000 P 0 IC 106242
DBG(4791151150)> CPU APPENDING: doAppendCycle (Exit) TRR 1 TSR 00000 TBR 00 CA 106242
DBG(4791151150)> CPU FINAL: Read2 (Actual) Read:  iefpFinalAddress=00106204  readData=000000100000
DBG(4791151150)> CPU FINAL: Read2 (Actual) Read:  iefpFinalAddress=00106205  readData=106242000000
DBG(4791151150)> CPU REGDUMPAQI: A=000000000000 Q=000000000000 IR:~BAR Carry Zero
DBG(4791151150)> CPU REGDUMPFLT: E=000 A=000000000000 Q=000000000000 0
DBG(4791151150)> CPU REGDUMPIDX: X[0]=000000 X[1]=000000 X[2]=000000 X[3]=000000
DBG(4791151150)> CPU REGDUMPIDX: X[4]=000000 X[5]=000000 X[6]=000000 X[7]=000000
DBG(4791151150)> CPU REGDUMPPR: PR0/ap: SNR=00000 RNR=0 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151150)> CPU REGDUMPPR: PR1/ab: SNR=00000 RNR=0 WORDNO=106204 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151150)> CPU REGDUMPPR: PR2/bp: SNR=00000 RNR=0 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151150)> CPU REGDUMPPR: PR3/bb: SNR=00000 RNR=0 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151150)> CPU REGDUMPPR: PR4/lp: SNR=00000 RNR=0 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151150)> CPU REGDUMPPR: PR5/lb: SNR=00000 RNR=0 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151150)> CPU REGDUMPPR: PR6/sp: SNR=00000 RNR=0 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151150)> CPU REGDUMPPR: PR7/sb: SNR=00000 RNR=0 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151150)> CPU REGDUMPPPR: PRR:1 PSR:00000 P:0 IC:106242
DBG(4791151150)> CPU REGDUMPDSBR: ADDR:00100736 BND:37777 U:1 STACK:0000

DBG(4791151152)> CPU APPENDING: doAppendCycle(Entry) thisCycle=INSTRUCTION_FETCH
DBG(4791151152)> CPU APPENDING: doAppendCycle(Entry) lastCycle=RTCD_OPERAND_FETCH
DBG(4791151152)> CPU APPENDING: doAppendCycle(Entry) CA 106242
DBG(4791151152)> CPU APPENDING: doAppendCycle(Entry) n= 2
DBG(4791151152)> CPU APPENDING: doAppendCycle(Entry) PPR.PRR=1 PPR.PSR=00000
DBG(4791151152)> CPU APPENDING: doAppendCycle(Entry) TPR.TRR=1 TPR.TSR=00000
DBG(4791151152)> CPU APPENDING: doAppendCycle(Entry) isb29 PRNO 1
DBG(4791151152)> CPU APPENDING: doAppendCycle(Entry) XSF 0
DBG(4791151152)> CPU APPENDING: doAppendCycle(A)
DBG(4791151152)> CPU APPENDING: fetchNSDW(0):segno=00000
DBG(4791151152)> CPU APPENDING: fetchNSDW(2):fetching SDW from 100736
DBG(4791151152)> CPU CORE: core_read2 20100736 000000000774 (fetchNSDW)
DBG(4791151152)> CPU CORE: core_read2 20100737 377777700000 (fetchNSDW)
DBG(4791151152)> CPU APPENDING: fetchNSDW(2):SDW0=ADDR=000000 R1=0 R2=7 R3=7 F=1 FC=0 BOUND=37777 R=1 E=1 W=1 P=1 U=1 G=1 C=0 EB=0
DBG(4791151152)> CPU APPENDING: doAppendCycle(A) R1 0 R2 7 R3 7 E 1
DBG(4791151152)> CPU APPENDING: doAppendCycle(B)
DBG(4791151152)> CPU APPENDING: doAppendCycle(C)
DBG(4791151152)> CPU APPENDING: doAppendCycle(D)
DBG(4791151152)> CPU APPENDING: doAppendCycle(G)
DBG(4791151152)> CPU APPENDING: doAppendCycle(H): FANP
DBG(4791151152)> CPU APPENDING: doAppendCycle(H): SDW->ADDR=00000000 CA=106242
DBG(4791151152)> CPU APPENDING: doAppendCycle(H:FANP): (00000:106242) finalAddress=00106242
DBG(4791151152)> CPU APPENDING: doAppendCycle(HI)
DBG(4791151152)> CPU CORE: core_read  20106242 000000011200 (INSTRUCTION_FETCH)
DBG(4791151152)> CPU CORE: core_read  20106243 000000011200 (INSTRUCTION_FETCH)
DBG(4791151152)> CPU APPENDING: doAppendCycle(L)
DBG(4791151152)> CPU APPENDING: doAppendCycle(KL)
DBG(4791151152)> CPU APPENDING: doAppendCycle(M)
DBG(4791151152)> CPU APPENDING: doAppendCycle (Exit) PRR 1 PSR 00000 P 0 IC 106242
DBG(4791151152)> CPU APPENDING: doAppendCycle (Exit) TRR 1 TSR 00000 TBR 00 CA 106242
DBG(4791151152)> CPU FINAL: Read2 (Actual) Read:  iefpFinalAddress=00106242  readData=000000011200
DBG(4791151152)> CPU FINAL: Read2 (Actual) Read:  iefpFinalAddress=00106243  readData=000000011200

DBG(4791151154)> CPU TRACE: 1: 00000:106242 1 000000011200 (NOP 000000) 000000 011(0) 0 1 0 00
DBG(4791151154)> CPU REGDUMPAQI: A=000000000000 Q=000000000000 IR:~BAR Carry Zero
DBG(4791151154)> CPU REGDUMPFLT: E=000 A=000000000000 Q=000000000000 0
DBG(4791151154)> CPU REGDUMPIDX: X[0]=000000 X[1]=000000 X[2]=000000 X[3]=000000
DBG(4791151154)> CPU REGDUMPIDX: X[4]=000000 X[5]=000000 X[6]=000000 X[7]=000000
DBG(4791151154)> CPU REGDUMPPR: PR0/ap: SNR=00000 RNR=1 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151154)> CPU REGDUMPPR: PR1/ab: SNR=00000 RNR=1 WORDNO=106204 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151154)> CPU REGDUMPPR: PR2/bp: SNR=00000 RNR=1 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151154)> CPU REGDUMPPR: PR3/bb: SNR=00000 RNR=1 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151154)> CPU REGDUMPPR: PR4/lp: SNR=00000 RNR=1 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151154)> CPU REGDUMPPR: PR5/lb: SNR=00000 RNR=1 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151154)> CPU REGDUMPPR: PR6/sp: SNR=00000 RNR=1 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151154)> CPU REGDUMPPR: PR7/sb: SNR=00000 RNR=1 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151154)> CPU REGDUMPPPR: PRR:1 PSR:00000 P:0 IC:106242
DBG(4791151154)> CPU REGDUMPDSBR: ADDR:00100736 BND:37777 U:1 STACK:0000

DBG(4791151156)> CPU APPENDING: doAppendCycle(Entry) thisCycle=INSTRUCTION_FETCH
DBG(4791151156)> CPU APPENDING: doAppendCycle(Entry) lastCycle=OPERAND_READ
DBG(4791151156)> CPU APPENDING: doAppendCycle(Entry) CA 106243
DBG(4791151156)> CPU APPENDING: doAppendCycle(Entry) n= 1
DBG(4791151156)> CPU APPENDING: doAppendCycle(Entry) PPR.PRR=1 PPR.PSR=00000
DBG(4791151156)> CPU APPENDING: doAppendCycle(Entry) TPR.TRR=1 TPR.TSR=00000
DBG(4791151156)> CPU APPENDING: doAppendCycle(Entry) XSF 0
DBG(4791151156)> CPU APPENDING: set TSR 00000 TRR 1
DBG(4791151156)> CPU APPENDING: doAppendCycle(A)
DBG(4791151156)> CPU APPENDING: fetchNSDW(0):segno=00000
DBG(4791151156)> CPU APPENDING: fetchNSDW(2):fetching SDW from 100736
DBG(4791151156)> CPU CORE: core_read2 20100736 000000000774 (fetchNSDW)
DBG(4791151156)> CPU CORE: core_read2 20100737 377777700000 (fetchNSDW)
DBG(4791151156)> CPU APPENDING: fetchNSDW(2):SDW0=ADDR=000000 R1=0 R2=7 R3=7 F=1 FC=0 BOUND=37777 R=1 E=1 W=1 P=1 U=1 G=1 C=0 EB=0
DBG(4791151156)> CPU APPENDING: doAppendCycle(A) R1 0 R2 7 R3 7 E 1
DBG(4791151156)> CPU APPENDING: doAppendCycle(B)
DBG(4791151156)> CPU APPENDING: doAppendCycle(F): transfer or instruction fetch
DBG(4791151156)> CPU APPENDING: doAppendCycle(D)
DBG(4791151156)> CPU APPENDING: doAppendCycle(G)
DBG(4791151156)> CPU APPENDING: doAppendCycle(H): FANP
DBG(4791151156)> CPU APPENDING: doAppendCycle(H): SDW->ADDR=00000000 CA=106243
DBG(4791151156)> CPU APPENDING: doAppendCycle(H:FANP): (00000:106243) finalAddress=00106243
DBG(4791151156)> CPU APPENDING: doAppendCycle(HI)
DBG(4791151156)> CPU CORE: core_read  20106243 000000011200 (INSTRUCTION_FETCH)
DBG(4791151156)> CPU APPENDING: doAppendCycle(L)
DBG(4791151156)> CPU APPENDING: doAppendCycle(KL)
DBG(4791151156)> CPU APPENDING: doAppendCycle(M)
DBG(4791151156)> CPU APPENDING: doAppendCycle (Exit) PRR 1 PSR 00000 P 0 IC 106243
DBG(4791151156)> CPU APPENDING: doAppendCycle (Exit) TRR 1 TSR 00000 TBR 00 CA 106243
DBG(4791151156)> CPU APPENDING: doAppendCycle (Exit) TRR 1 TSR 00000 TBR 00 CA 106243
DBG(4791151156)> CPU FINAL: Read (Actual) Read:  iefpFinalAddress=00106243  readData=000000011200

DBG(4791151158)> CPU TRACE: 1: 00000:106243 1 000000011200 (NOP 000000) 000000 011(0) 0 1 0 00
DBG(4791151158)> CPU REGDUMPAQI: A=000000000000 Q=000000000000 IR:~BAR Carry Zero
DBG(4791151158)> CPU REGDUMPFLT: E=000 A=000000000000 Q=000000000000 0
DBG(4791151158)> CPU REGDUMPIDX: X[0]=000000 X[1]=000000 X[2]=000000 X[3]=000000
DBG(4791151158)> CPU REGDUMPIDX: X[4]=000000 X[5]=000000 X[6]=000000 X[7]=000000
DBG(4791151158)> CPU REGDUMPPR: PR0/ap: SNR=00000 RNR=1 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151158)> CPU REGDUMPPR: PR1/ab: SNR=00000 RNR=1 WORDNO=106204 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151158)> CPU REGDUMPPR: PR2/bp: SNR=00000 RNR=1 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151158)> CPU REGDUMPPR: PR3/bb: SNR=00000 RNR=1 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151158)> CPU REGDUMPPR: PR4/lp: SNR=00000 RNR=1 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151158)> CPU REGDUMPPR: PR5/lb: SNR=00000 RNR=1 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151158)> CPU REGDUMPPR: PR6/sp: SNR=00000 RNR=1 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151158)> CPU REGDUMPPR: PR7/sb: SNR=00000 RNR=1 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151158)> CPU REGDUMPPPR: PRR:1 PSR:00000 P:0 IC:106243
DBG(4791151158)> CPU REGDUMPDSBR: ADDR:00100736 BND:37777 U:1 STACK:0000

DBG(4791151160)> CPU APPENDING: doAppendCycle(Entry) thisCycle=INSTRUCTION_FETCH
DBG(4791151160)> CPU APPENDING: doAppendCycle(Entry) lastCycle=OPERAND_READ
DBG(4791151160)> CPU APPENDING: doAppendCycle(Entry) CA 106244
DBG(4791151160)> CPU APPENDING: doAppendCycle(Entry) n= 2
DBG(4791151160)> CPU APPENDING: doAppendCycle(Entry) PPR.PRR=1 PPR.PSR=00000
DBG(4791151160)> CPU APPENDING: doAppendCycle(Entry) TPR.TRR=1 TPR.TSR=00000
DBG(4791151160)> CPU APPENDING: doAppendCycle(Entry) XSF 0
DBG(4791151160)> CPU APPENDING: set TSR 00000 TRR 1
DBG(4791151160)> CPU APPENDING: doAppendCycle(A)
DBG(4791151160)> CPU APPENDING: fetchNSDW(0):segno=00000
DBG(4791151160)> CPU APPENDING: fetchNSDW(2):fetching SDW from 100736
DBG(4791151160)> CPU CORE: core_read2 20100736 000000000774 (fetchNSDW)
DBG(4791151160)> CPU CORE: core_read2 20100737 377777700000 (fetchNSDW)
DBG(4791151160)> CPU APPENDING: fetchNSDW(2):SDW0=ADDR=000000 R1=0 R2=7 R3=7 F=1 FC=0 BOUND=37777 R=1 E=1 W=1 P=1 U=1 G=1 C=0 EB=0
DBG(4791151160)> CPU APPENDING: doAppendCycle(A) R1 0 R2 7 R3 7 E 1
DBG(4791151160)> CPU APPENDING: doAppendCycle(B)
DBG(4791151160)> CPU APPENDING: doAppendCycle(F): transfer or instruction fetch
DBG(4791151160)> CPU APPENDING: doAppendCycle(D)
DBG(4791151160)> CPU APPENDING: doAppendCycle(G)
DBG(4791151160)> CPU APPENDING: doAppendCycle(H): FANP
DBG(4791151160)> CPU APPENDING: doAppendCycle(H): SDW->ADDR=00000000 CA=106244
DBG(4791151160)> CPU APPENDING: doAppendCycle(H:FANP): (00000:106244) finalAddress=00106244
DBG(4791151160)> CPU APPENDING: doAppendCycle(HI)
DBG(4791151160)> CPU CORE: core_read  20106244 000000004200 (INSTRUCTION_FETCH)
DBG(4791151160)> CPU CORE: core_read  20106245 100153450200 (INSTRUCTION_FETCH)
DBG(4791151160)> CPU APPENDING: doAppendCycle(L)
DBG(4791151160)> CPU APPENDING: doAppendCycle(KL)
DBG(4791151160)> CPU APPENDING: doAppendCycle(M)
DBG(4791151160)> CPU APPENDING: doAppendCycle (Exit) PRR 1 PSR 00000 P 0 IC 106244
DBG(4791151160)> CPU APPENDING: doAppendCycle (Exit) TRR 1 TSR 00000 TBR 00 CA 106244
DBG(4791151160)> CPU FINAL: Read2 (Actual) Read:  iefpFinalAddress=00106244  readData=000000004200
DBG(4791151160)> CPU FINAL: Read2 (Actual) Read:  iefpFinalAddress=00106245  readData=100153450200

DBG(4791151162)> CPU TRACE: 1: 00000:106244 1 000000004200 (MME2 000000) 000000 004(0) 0 1 0 00
DBG(4791151162)> CPU FAULT: Fault 21(025), sub 0(00), dfc N, 'Master Mode Entry 2 (mme2)'
DBG(4791151162)> CPU FAULT: 1: 00000:106244 1 000000004200 (MME2 000000) 000000 004(0) 0 1 0 00
DBG(4791151162)> CPU TRACE: MIF 0

DBG(4791151163)> CPU CORE: core_read2 20000152 100600657000 (sim_instr)
DBG(4791151163)> CPU CORE: core_read2 20000153 106306717000 (sim_instr)

DBG(4791151165)> CPU TRACE: 1: 106244 100600657000 (SCU 100600) 100600 657(0) 0 0 0 00
DBG(4791151165)> CPU CORE: core_write 20100600 100000000011 (Write8)
DBG(4791151165)> CPU CORE: core_write 20100601 000000000053 (Write8)
DBG(4791151165)> CPU CORE: core_write 20100602 100000000100 (Write8)
DBG(4791151165)> CPU CORE: core_write 20100603 000000000000 (Write8)
DBG(4791151165)> CPU CORE: core_write 20100604 106244500200 (Write8)
DBG(4791151165)> CPU CORE: core_write 20100605 000000000000 (Write8)
DBG(4791151165)> CPU CORE: core_write 20100606 000000004200 (Write8)
DBG(4791151165)> CPU CORE: core_write 20100607 100153450200 (Write8)
DBG(4791151165)> CPU FINAL: Write(Actual) Write:      abs address=00100600 writeData=100000000011
DBG(4791151165)> CPU FINAL: Write(Actual) Write:      abs address=00100601 writeData=000000000053
DBG(4791151165)> CPU FINAL: Write(Actual) Write:      abs address=00100602 writeData=100000000100
DBG(4791151165)> CPU FINAL: Write(Actual) Write:      abs address=00100603 writeData=000000000000
DBG(4791151165)> CPU FINAL: Write(Actual) Write:      abs address=00100604 writeData=106244500200
DBG(4791151165)> CPU FINAL: Write(Actual) Write:      abs address=00100605 writeData=000000000000
DBG(4791151165)> CPU FINAL: Write(Actual) Write:      abs address=00100606 writeData=000000004200
DBG(4791151165)> CPU FINAL: Write(Actual) Write:      abs address=00100607 writeData=100153450200
DBG(4791151165)> CPU REGDUMPAQI: A=000000000000 Q=000000000000 IR:~BAR Carry Zero
DBG(4791151165)> CPU REGDUMPFLT: E=000 A=000000000000 Q=000000000000 0
DBG(4791151165)> CPU REGDUMPIDX: X[0]=000000 X[1]=000000 X[2]=000000 X[3]=000000
DBG(4791151165)> CPU REGDUMPIDX: X[4]=000000 X[5]=000000 X[6]=000000 X[7]=000000
DBG(4791151165)> CPU REGDUMPPR: PR0/ap: SNR=00000 RNR=1 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151165)> CPU REGDUMPPR: PR1/ab: SNR=00000 RNR=1 WORDNO=106204 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151165)> CPU REGDUMPPR: PR2/bp: SNR=00000 RNR=1 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151165)> CPU REGDUMPPR: PR3/bb: SNR=00000 RNR=1 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151165)> CPU REGDUMPPR: PR4/lp: SNR=00000 RNR=1 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151165)> CPU REGDUMPPR: PR5/lb: SNR=00000 RNR=1 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151165)> CPU REGDUMPPR: PR6/sp: SNR=00000 RNR=1 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151165)> CPU REGDUMPPR: PR7/sb: SNR=00000 RNR=1 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151165)> CPU REGDUMPPPR: PRR:0 PSR:00000 P:0 IC:106244
DBG(4791151165)> CPU REGDUMPDSBR: ADDR:00100736 BND:37777 U:1 STACK:0000

DBG(4791151167)> CPU TRACE: 1: 106244 106306717000 (XED 106306) 106306 717(0) 0 0 0 00
DBG(4791151167)> CPU CORE: core_read2 20106306 100230357000 (Read2)
DBG(4791151167)> CPU CORE: core_read2 20106307 106245710000 (Read2)
DBG(4791151167)> CPU FINAL: Read2 (Actual) Read:       abs address=00106306  readData=100230357000
DBG(4791151167)> CPU FINAL: Read2 (Actual) Read:       abs address=00106307  readData=106245710000
DBG(4791151167)> CPU REGDUMPAQI: A=000000000000 Q=000000000000 IR:~BAR Carry Zero
DBG(4791151167)> CPU REGDUMPFLT: E=000 A=000000000000 Q=000000000000 0
DBG(4791151167)> CPU REGDUMPIDX: X[0]=000000 X[1]=000000 X[2]=000000 X[3]=000000
DBG(4791151167)> CPU REGDUMPIDX: X[4]=000000 X[5]=000000 X[6]=000000 X[7]=000000
DBG(4791151167)> CPU REGDUMPPR: PR0/ap: SNR=00000 RNR=1 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151167)> CPU REGDUMPPR: PR1/ab: SNR=00000 RNR=1 WORDNO=106204 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151167)> CPU REGDUMPPR: PR2/bp: SNR=00000 RNR=1 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151167)> CPU REGDUMPPR: PR3/bb: SNR=00000 RNR=1 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151167)> CPU REGDUMPPR: PR4/lp: SNR=00000 RNR=1 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151167)> CPU REGDUMPPR: PR5/lb: SNR=00000 RNR=1 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151167)> CPU REGDUMPPR: PR6/sp: SNR=00000 RNR=1 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151167)> CPU REGDUMPPR: PR7/sb: SNR=00000 RNR=1 WORDNO=000000 BITNO:00 ARCHAR:0 ARBITNO:00
DBG(4791151167)> CPU REGDUMPPPR: PRR:0 PSR:00000 P:0 IC:106244
DBG(4791151167)> CPU REGDUMPDSBR: ADDR:00100736 BND:37777 U:1 STACK:0000

DBG(4791151169)> CPU APPENDING: doAppendCycle(Entry) thisCycle=INSTRUCTION_FETCH
DBG(4791151169)> CPU APPENDING: doAppendCycle(Entry) lastCycle=OPERAND_READ
DBG(4791151169)> CPU APPENDING: doAppendCycle(Entry) CA 106245
DBG(4791151169)> CPU APPENDING: doAppendCycle(Entry) n= 1
DBG(4791151169)> CPU APPENDING: doAppendCycle(Entry) PPR.PRR=1 PPR.PSR=00000
DBG(4791151169)> CPU APPENDING: doAppendCycle(Entry) TPR.TRR=1 TPR.TSR=00000
DBG(4791151169)> CPU APPENDING: doAppendCycle(Entry) XSF 0
DBG(4791151169)> CPU APPENDING: set TSR 00000 TRR 1
DBG(4791151169)> CPU APPENDING: doAppendCycle(A)
DBG(4791151169)> CPU APPENDING: fetchNSDW(0):segno=00000
DBG(4791151169)> CPU APPENDING: fetchNSDW(2):fetching SDW from 100736
DBG(4791151169)> CPU CORE: core_read2 20100736 000000000774 (fetchNSDW)
DBG(4791151169)> CPU CORE: core_read2 20100737 377777700000 (fetchNSDW)
DBG(4791151169)> CPU APPENDING: fetchNSDW(2):SDW0=ADDR=000000 R1=0 R2=7 R3=7 F=1 FC=0 BOUND=37777 R=1 E=1 W=1 P=1 U=1 G=1 C=0 EB=0
DBG(4791151169)> CPU APPENDING: doAppendCycle(A) R1 0 R2 7 R3 7 E 1
DBG(4791151169)> CPU APPENDING: doAppendCycle(B)
DBG(4791151169)> CPU APPENDING: doAppendCycle(F): transfer or instruction fetch
DBG(4791151169)> CPU APPENDING: doAppendCycle(D)
DBG(4791151169)> CPU APPENDING: doAppendCycle(G)
DBG(4791151169)> CPU APPENDING: doAppendCycle(H): FANP
DBG(4791151169)> CPU APPENDING: doAppendCycle(H): SDW->ADDR=00000000 CA=106245
DBG(4791151169)> CPU APPENDING: doAppendCycle(H:FANP): (00000:106245) finalAddress=00106245
DBG(4791151169)> CPU APPENDING: doAppendCycle(HI)
DBG(4791151169)> CPU CORE: core_read  20106245 100153450200 (INSTRUCTION_FETCH)
DBG(4791151169)> CPU APPENDING: doAppendCycle(L)
DBG(4791151169)> CPU APPENDING: doAppendCycle(KL)
DBG(4791151169)> CPU APPENDING: doAppendCycle(M)
DBG(4791151169)> CPU APPENDING: doAppendCycle (Exit) PRR 1 PSR 00000 P 0 IC 106245
DBG(4791151169)> CPU APPENDING: doAppendCycle (Exit) TRR 1 TSR 00000 TBR 00 CA 106245
DBG(4791151169)> CPU FINAL: Read (Actual) Read:  iefpFinalAddress=00106245  readData=100153450200

DBG(4791151171)> CPU TRACE: 1: 00000:106245 1 100153450200 (STZ 100153) 100153 450(0) 0 1 0 00
DBG(4791151171)> CPU APPENDING: doAppendCycle(Entry) thisCycle=OPERAND_STORE
DBG(4791151171)> CPU APPENDING: doAppendCycle(Entry) lastCycle=INSTRUCTION_FETCH
DBG(4791151171)> CPU APPENDING: doAppendCycle(Entry) CA 100153
DBG(4791151171)> CPU APPENDING: doAppendCycle(Entry) n= 1
DBG(4791151171)> CPU APPENDING: doAppendCycle(Entry) PPR.PRR=1 PPR.PSR=00000
DBG(4791151171)> CPU APPENDING: doAppendCycle(Entry) TPR.TRR=1 TPR.TSR=00000
DBG(4791151171)> CPU APPENDING: doAppendCycle(Entry) XSF 0
DBG(4791151171)> CPU APPENDING: set TSR 00000 TRR 1
DBG(4791151171)> CPU APPENDING: doAppendCycle(A)
DBG(4791151171)> CPU APPENDING: fetchNSDW(0):segno=00000
DBG(4791151171)> CPU APPENDING: fetchNSDW(2):fetching SDW from 100736
DBG(4791151171)> CPU CORE: core_read2 20100736 000000000774 (fetchNSDW)
DBG(4791151171)> CPU CORE: core_read2 20100737 377777700000 (fetchNSDW)
DBG(4791151171)> CPU APPENDING: fetchNSDW(2):SDW0=ADDR=000000 R1=0 R2=7 R3=7 F=1 FC=0 BOUND=37777 R=1 E=1 W=1 P=1 U=1 G=1 C=0 EB=0
DBG(4791151171)> CPU APPENDING: doAppendCycle(A) R1 0 R2 7 R3 7 E 1
DBG(4791151171)> CPU APPENDING: doAppendCycle(B)
DBG(4791151171)> CPU APPENDING: doAppendCycle(B):STR-OP
DBG(4791151171)> CPU APPENDING: doAppendCycle(G)
DBG(4791151171)> CPU APPENDING: doAppendCycle(G) acvFaults
DBG(4791151171)> CPU FAULT: Fault 20(024), sub 1024(02000), dfc N, 'ACV fault'

ACV5 not in write bracket

bracket is 0 7 7
ring is 1

DBG(4791151171)> CPU FAULT: 1: 00000:106245 1 100153450200 (STZ 100153) 100153 450(0) 0 1 0 00
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