CAC 2016-08-28
BAR mode
pa865 test-01a bar insts bar-000002
***dsbr*** addr= 00110000 bnd= 00001 u= 1 stack= 0000
test start 101107 patch 101326 subtest loop point 101232
this subtest is checking instruction addressing
from a bar controlled area within a privileged
segment.
prime results c(y+0) c(y+1) c(y+2) c(y+3)
s/b 000001450011 000000000015 000001000100 000000000000
was 000001450021 000000000015 000001000100 000000000000
c(y+4) c(y+5) c(y+6) c(y+7)
s/b 000014400000 110014000000 110014002000 000000000000
was 000014400000 110014000000 110014002000 000000000000
faults s/b was
derail -000014 derail - 000014
function in error -
the base address register probably did not
add in correctly
y to y+7 is scu data stored on the expected fault
DBG(2189897951)> CPU1 APPENDING: doAppendCycle(Entry) thisCycle=INSTRUCTION_FETCH
DBG(2189897951)> CPU1 APPENDING: fetchNSDW(2):SDW0=ADDR=110000 R1=0 R2=0 R3=0 F=1 FC=0 BOUND=1 R=1 E=1 W=1 P=1 U=1 G=1 C=0 EB=0
DBG(2189897951)> CPU1 APPENDING: loadSDWAM: SDWAM disabled
DBG(2189897951)> CPU1 APPENDING: doAppendCycle(A) R1 0 R2 0 R3 0
DBG(2189897951)> CPU1 APPENDING: doAppendCycle(B)
DBG(2189897951)> CPU1 APPENDING: doAppendCycle(F): transfer or instruction fetch
DBG(2189897951)> CPU1 APPENDING: doAppendCycle(D)
DBG(2189897951)> CPU1 APPENDING: doAppendCycle(G)
DBG(2189897951)> CPU1 APPENDING: doAppendCycle(H): FANP
DBG(2189897951)> CPU1 APPENDING: doAppendCycle(H): SDW->ADDR=00110000 TPR.CA=000015
DBG(2189897951)> CPU1 APPENDING: doAppendCycle(H:FANP): (00001:000015) finalAddress=00110015
DBG(2189897951)> CPU1 APPENDING: doAppendCycle(HI)
DBG(2189897951)> CPU1 APPENDING: doAppendCycle(KLM)
DBG(2189897951)> CPU1 APPENDING: doAppendCycle(KLM) TPR.TSR 00001 TPR.CA 000015
DBG(2189897951)> CPU1 APPENDING: doAppendCycle(KLM) TPR.TRR 0 SDW.P 1 PPR.P 1
DBG(2189897951)> CPU1 CORE: core_read 20110015 000000000000 (Read)
DBG(2189897951)> CPU1 APPENDING: Read (Actual) Read: bar iefpFinalAddress=00110015 readData=000000000000
DBG(2189897953)> CPU1 TRACE: 1: 00001:000000|000014 0 110014002000 (DRL 110014) 110014 002(0) 0 0 0 00
DBG(2189897953)> CPU1 FAULT: Fault 6(06), sub 0(00), dfc N, 'drl'
DBG(2189897953)> CPU1 FAULT: 1: 00001:000000|000014 0 110014002000 (DRL 110014) 110014 002(0) 0 0 0 00
DBG(2189897954)> CPU1 CORE: core_read2 20000114 020320657200 (sim_instr)
DBG(2189897954)> CPU1 CORE: core_read2 20000115 017175710200 (sim_instr)
DBG(2189897956)> CPU1 TRACE: 1: 00000|000014 020320657200 (SCU 020320) 020320 657(0) 0 1 0 00
DBG(2189897956)> CPU1 ADDRMOD: doComputedAddressFormation(Entry): operType:writeCYblock8 TPR.CA=020320
DBG(2189897956)> CPU1 ADDRMOD: doComputedAddressFormation(Entry): CT_HOLD 0
DBG(2189897956)> CPU1 ADDRMOD: doComputedAddressFormation(startCA): TAG=00() Tm=0 Td=0
DBG(2189897956)> CPU1 ADDRMOD: writeOperands(SCU 020320):mne=scu flags=24020
DBG(2189897956)> CPU1 CORE: core_write 20020320 000001450021 (Write)
DBG(2189897956)> CPU1 FINAL: Write(Actual) Write: abs address=00020320 writeData=000001450021
The last append operation was fetching the instruction in FANP mode -- Appending and BAR modes are set.
ISOLTS says FABS should be set, not FANP.
If the code is changed to always set FABS, the test advances to test-03a
pa865 test-03a inhibit bar-000002
***dsbr*** addr= 00110000 bnd= 00001 u= 1 stack= 0000
test start 101657 patch 102043 subtest loop point 101732
this subtest is checking inhibited instruction
execution while in the absolute,privileged, and
bar mode
prime results c(y+0) c(y+1) c(y+2) c(y+3)
s/b 000001450021 000000000011 000001000100 000000000000
was 000001450011 000000000011 000001000100 000000000000
c(y+4) c(y+5) c(y+6) c(y+7)
s/b 000016400000 110015000500 110014011000 110015011000
was 000016400000 110015000100 110015011000 110015011000
faults s/b was
timer-run-out -000016 timer-run-out - 000016
Now the problem is reversed; it saw FABS and expected FANP.
DBG(5073505823)> CPU1 APPENDING: fetchNSDW(2):SDW0=ADDR=110000 R1=0 R2=0 R3=0 F=1 FC=0 BOUND=2 R=1 E=1 W=1 P=1 U=1 G=1 C=0 EB=0
DBG(5073505823)> CPU1 APPENDING: loadSDWAM: SDWAM disabled
DBG(5073505823)> CPU1 APPENDING: doAppendCycle(A) R1 0 R2 0 R3 0
DBG(5073505823)> CPU1 APPENDING: doAppendCycle(B)
DBG(5073505823)> CPU1 APPENDING: doAppendCycle(F): transfer or instruction fetch
DBG(5073505823)> CPU1 APPENDING: doAppendCycle(D)
DBG(5073505823)> CPU1 APPENDING: doAppendCycle(G)
DBG(5073505823)> CPU1 APPENDING: doAppendCycle(H): FANP
DBG(5073505823)> CPU1 APPENDING: doAppendCycle(H): SDW->ADDR=00110000 TPR.CA=000015
DBG(5073505823)> CPU1 APPENDING: doAppendCycle(H:FANP): (00001:000015) finalAddress=00110015
DBG(5073505823)> CPU1 APPENDING: doAppendCycle(HI)
DBG(5073505823)> CPU1 APPENDING: doAppendCycle(KLM)
DBG(5073505823)> CPU1 APPENDING: doAppendCycle(KLM) TPR.TSR 00001 TPR.CA 000015
DBG(5073505823)> CPU1 APPENDING: doAppendCycle(KLM) TPR.TRR 0 SDW.P 1 PPR.P 1
DBG(5073505823)> CPU1 CORE: core_read 20110015 110015011000 (Read)
DBG(5073505823)> CPU1 APPENDING: Read (Actual) Read: bar iefpFinalAddress=00110015 readData=110015011000
DBG(5073505825)> CPU1 TRACE: 1: 00001:000000|000015 0 110015011000 (NOP 110015) 110015 011(0) 0 0 0 00
DBG(5073505825)> CPU1 ADDRMOD: doComputedAddressFormation(Entry): operType:prepareCA TPR.CA=110015
DBG(5073505825)> CPU1 ADDRMOD: doComputedAddressFormation(Entry): CT_HOLD 0
DBG(5073505825)> CPU1 ADDRMOD: doComputedAddressFormation(startCA): TAG=00() Tm=0 Td=0
DBG(5073505825)> CPU1 REGDUMPAQI: A=000000000000 Q=000027700000 IR:Zero
DBG(5073505827)> CPU1 FAULT: Fault 4(04), sub 0(00), dfc N, 'Timer runout'
DBG(5073505827)> CPU1 FAULT: 1: 00001:000000|000016 0 110015011000 (NOP 110015) 110015 011(0) 0 0 0 00
DBG(5073505828)> CPU1 CORE: core_read2 20000110 020320657200 (sim_instr)
DBG(5073505828)> CPU1 CORE: core_read2 20000111 017162710200 (sim_instr)
DBG(5073505830)> CPU1 TRACE: 1: 00000|000016 020320657200 (SCU 020320) 020320 657(0) 0 1 0 00
DBG(5073505830)> CPU1 ADDRMOD: doComputedAddressFormation(Entry): operType:writeCYblock8 TPR.CA=020320
DBG(5073505830)> CPU1 ADDRMOD: doComputedAddressFormation(Entry): CT_HOLD 0
DBG(5073505830)> CPU1 ADDRMOD: doComputedAddressFormation(startCA): TAG=00() Tm=0 Td=0
DBG(5073505830)> CPU1 ADDRMOD: writeOperands(SCU 020320):mne=scu flags=24020
DBG(5073505830)> CPU1 CORE: core_write 20020320 000001450011 (Write)
DBG(5073505830)> CPU1 FINAL: Write(Actual) Write: abs address=00020320 writeData=000001450011
Unclear what the difference is; the last append cycle was the same -- an instruction fetch in append+BAR mode.
I wonder is the PREPARE_CA functionality in the NOP instruction is supposed to affect the Append mode state bits
even if append mode was not explicitly invoked.
page revision: 0, last edited: 28 Aug 2016 17:43