CAC 2016-02-20

round_robin

"         The first steps of the initialized processor ...
"
"         The processor reaches this point still in absolute mode. The
"         DBR must be loaded, and then appending mode ...

          inhibit   on        <+><+><+><+><+><+><+><+><+><+><+><+>
first_steps:
          sti       indic-*,ic          save indicators
          lda       indic-*,ic          pick up indicators
          cana      scu.ir.abs,dl       in abs mode?
          tze       gcoserr-*,ic        if not, CPU is in wrong mode
set_cache_off:
          lcpr      0,02                turn cache off before we get into trouble.
          eax3      0
          eax7      0                   read processor switches
          ldx6      switch_test-*,ic    this code executes in ABSOLUTE MODE
          ldx5      switch_discrep-*,ic ..
          ldx4      switch_data-*,ic    ..

DBG(190831072)> CPU TRACE: 1: 320050 000346754204 (STI 000346,IC) 000346 754(0) 0 1 0 04
DBG(190831072)> CPU FINAL: Write(Actual) Write:      abs address=00320416 writeData=000000000220

DBG(190831076)> CPU TRACE: 1: 320051 000345235204 (LDA 000345,IC) 000345 235(0) 0 1 0 04^M
DBG(190831076)> CPU FINAL: Read (Actual) Read:       abs address=00320416  readData=000000000220
A=000000000220

DBG(190831080)> CPU TRACE: 1: 320052 000020315207 (CANA 000020,DL) 000020 315(0) 0 1 0 07
DBG(190831080)> CPU REGDUMPAQI: A=000000000220 Q=000000000000 IR:Abs ~BAR

DBG(190831084)> CPU TRACE: 1: 320053 000120600204 (TZE 000120,IC) 000120 600(0) 0 1 0 04

DBG(190831088)> CPU TRACE: 1: 320054 320372674202 (LCPR 320372,QU) 320372 674(0) 0 1 0 02

DBG(190831092)> CPU TRACE: 1: 320055 000000623200 (EAX3 000000) 000000 623(0) 0 1 0 00
X[3]=000000

DBG(190831096)> CPU TRACE: 1: 320056 000000627200 (EAX7 000000) 000000 627(0) 0 1 0 00
X[7]=000000

DBG(190831100)> CPU TRACE: 1: 320057 000326226204 (LDX6 000326,IC) 000326 226(0) 0 1 0 04
X[6]=120305

DBG(190831104)> CPU TRACE: 1: 320060 000327225204 (LDX5 000327,IC) 000327 225(0) 0 1 0 04
X[5]=120312

DBG(190831108)> CPU TRACE: 1: 320061 000323224204 (LDX4 000323,IC) 000323 224(0) 0 1 0 04
X[4]=120300

swtest1:  rsw       0,7                 read processor switches
          sta       0,4                 and save
          era       0,6                 generate discrepancy data
          sta       0,5                 and store
          eax5      1,5                 ..
          eax6      1,6                 ..
          cmpx7     2,du                was this an rsw (2)?
          tnz       swtest2-*,ic        xfer if no
          lda       0,4                 yes, load rsw (2) data
          lrl       30                  position  cpu type in AL
          ana       3,dl                and out all but  cpu type
          tze       swtest2-*,ic        xfer if L68 or DPS cpu
          eax3      0,al                copy cpu type into x3
          tra       swtest3-*,ic        and go check switches

DBG(190831112)> CPU TRACE: 1: 320062 000000231217 (RSW 000000,7) 000000 231(0) 0 1 0 17
A=024000717200

DBG(190831116)> CPU TRACE: 1: 320063 000000755214 (STA 000000,4) 000000 755(0) 0 1 0 14
DBG(190831116)> CPU FINAL: Write(Actual) Write:      abs address=00120300 writeData=024000717200

DBG(190831120)> CPU TRACE: 1: 320064 000000675216 (ERA 000000,6) 000000 675(0) 0 1 0 16
DBG(190831120)> CPU FINAL: Read (Actual) Read:       abs address=00120305  readData=024000717200
A=000000000000

DBG(190831124)> CPU TRACE: 1: 320065 000000755215 (STA 000000,5) 000000 755(0) 0 1 0 15
DBG(190831124)> CPU FINAL: Write(Actual) Write:      abs address=00120312 writeData=000000000000

DBG(190831128)> CPU TRACE: 1: 320066 000001625215 (EAX5 000001,5) 000001 625(0) 0 1 0 15
X[5]=120313

DBG(190831132)> CPU TRACE: 1: 320067 000001626216 (EAX6 000001,6) 000001 626(0) 0 1 0 16
X[6]=120306

DBG(190831136)> CPU TRACE: 1: 320070 000002107203 (CMPX7 000002,DU) 000002 107(0) 0 1 0 03
Neg

DBG(190831140)> CPU TRACE: 1: 320071 000007601204 (TNZ 000007,IC) 000007 601(0) 0 1 0 04

swtest2:  cmpx7     4,du                was last instuction rsw (4)?
          tze       swtest3-*,ic        yes, go check switches
          eax4      1,4                 increment rsw data storage
          eax7      1,7                 loop until finished
          tra       swtest1-*,ic        ..

DBG(190831144)> CPU TRACE: 1: 320100 000004107203 (CMPX7 000004,DU) 000004 107(0) 0 1 0 03
Neg

DBG(190831148)> CPU TRACE: 1: 320101 000004600204 (TZE 000004,IC) 000004 600(0) 0 1 0 04

DBG(190831152)> CPU TRACE: 1: 320102 000001624214 (EAX4 000001,4) 000001 624(0) 0 1 0 14
X[4]=120301

DBG(190831156)> CPU TRACE: 1: 320103 000001627217 (EAX7 000001,7) 000001 627(0) 0 1 0 17
X[7]=000001

DBG(190831160)> CPU TRACE: 1: 320104 777756710204 (TRA 777756,IC) 777756 710(0) 0 1 0 04

swtest1:  rsw       0,7                 read processor switches
          sta       0,4                 and save
          era       0,6                 generate discrepancy data
          sta       0,5                 and store
          eax5      1,5                 ..
          eax6      1,6                 ..
          cmpx7     2,du                was this an rsw (2)?
          tnz       swtest2-*,ic        xfer if no
          lda       0,4                 yes, load rsw (2) data
          lrl       30                  position  cpu type in AL
          ana       3,dl                and out all but  cpu type
          tze       swtest2-*,ic        xfer if L68 or DPS cpu
          eax3      0,al                copy cpu type into x3
          tra       swtest3-*,ic        and go check switches

DBG(190831164)> CPU TRACE: 1: 320062 000000231217 (RSW 000000,7) 000000 231(0) 0 1 0 17
A=067167267367  (configuration switches for ports A, B, C, D)
port A ADR 0 PORT_ENABLE 1 INIT_ENB 0 IF_ENB 1 MEM 7
port B ADR 1 PORT_ENABLE 1 INIT_ENB 0 IF_ENB 1 MEM 7
port C ADR 2 PORT_ENABLE 1 INIT_ENB 0 IF_ENB 1 MEM 7
port D ADR 3 PORT_ENABLE 1 INIT_ENB 0 IF_ENB 1 MEM 7

DBG(190831168)> CPU TRACE: 1: 320063 000000755214 (STA 000000,4) 000000 755(0) 0 1 0 14
DBG(190831168)> CPU FINAL: Write(Actual) Write:      abs address=00120301 writeData=067167267367

DBG(190831172)> CPU TRACE: 1: 320064 000000675216 (ERA 000000,6) 000000 675(0) 0 1 0 16
DBG(190831172)> CPU FINAL: Read (Actual) Read:       abs address=00120306  readData=067167267367
A=000000000000 Zero

DBG(190831176)> CPU TRACE: 1: 320065 000000755215 (STA 000000,5) 000000 755(0) 0 1 0 15

DBG(190831180)> CPU TRACE: 1: 320066 000001625215 (EAX5 000001,5) 000001 625(0) 0 1 0 15
X[5]=120314

DBG(190831184)> CPU TRACE: 1: 320067 000001626216 (EAX6 000001,6) 000001 626(0) 0 1 0 16
X[6]=120307

DBG(190831188)> CPU TRACE: 1: 320070 000002107203 (CMPX7 000002,DU) 000002 107(0) 0 1 0 03
X[7]=000001 Neg

DBG(190831192)> CPU TRACE: 1: 320071 000007601204 (TNZ 000007,IC) 000007 601(0) 0 1 0 04

swtest2:  cmpx7     4,du                was last instuction rsw (4)?
          tze       swtest3-*,ic        yes, go check switches
          eax4      1,4                 increment rsw data storage
          eax7      1,7                 loop until finished
          tra       swtest1-*,ic        ..

DBG(190831196)> CPU TRACE: 1: 320100 000004107203 (CMPX7 000004,DU) 000004 107(0) 0 1 0 03
X[7]=000001

DBG(190831200)> CPU TRACE: 1: 320101 000004600204 (TZE 000004,IC) 000004 600(0) 0 1 0 04

DBG(190831204)> CPU TRACE: 1: 320102 000001624214 (EAX4 000001,4) 000001 624(0) 0 1 0 14
X[4]=120302

DBG(190831208)> CPU TRACE: 1: 320103 000001627217 (EAX7 000001,7) 000001 627(0) 0 1 0 17
X[7]=000002

DBG(190831212)> CPU TRACE: 1: 320104 777756710204 (TRA 777756,IC) 777756 710(0) 0 1 0 04

swtest1:  rsw       0,7                 read processor switches
          sta       0,4                 and save
          era       0,6                 generate discrepancy data
          sta       0,5                 and store
          eax5      1,5                 ..
          eax6      1,6                 ..
          cmpx7     2,du                was this an rsw (2)?
          tnz       swtest2-*,ic        xfer if no
          lda       0,4                 yes, load rsw (2) data
          lrl       30                  position  cpu type in AL
          ana       3,dl                and out all but  cpu type
          tze       swtest2-*,ic        xfer if L68 or DPS cpu
          eax3      0,al                copy cpu type into x3
          tra       swtest3-*,ic        and go check switches

DBG(190831216)> CPU TRACE: 1: 320062 000000231217 (RSW 000000,7) 000000 231(0) 0 1 0 17
A=010120716001

PORT A 4 word interface
PORT B 4 word interface
PORT A 4 word interface
PORT D 4 word interface
DPS8M
FLTBASE 2
ID PROM installed
BCD OPTION
DPS OPTION
8K cache
DPS8M
Virtual mode
NPL
Speed 8/70
CPU #1

DBG(190831220)> CPU TRACE: 1: 320063 000000755214 (STA 000000,4) 000000 755(0) 0 1 0 14
DBG(190831220)> CPU FINAL: Write(Actual) Write:      abs address=00120302 writeData=010120716001

DBG(190831224)> CPU TRACE: 1: 320064 000000675216 (ERA 000000,6) 000000 675(0) 0 1 0 16
DBG(190831224)> CPU FINAL: Read (Actual) Read:       abs address=00120307  readData=010120716001
A=000000000000

DBG(190831228)> CPU TRACE: 1: 320065 000000755215 (STA 000000,5) 000000 755(0) 0 1 0 15
DBG(190831228)> CPU FINAL: Write(Actual) Write:      abs address=00120314 writeData=000000000000

DBG(190831232)> CPU TRACE: 1: 320066 000001625215 (EAX5 000001,5) 000001 625(0) 0 1 0 15
X[5]=120315

DBG(190831236)> CPU TRACE: 1: 320067 000001626216 (EAX6 000001,6) 000001 626(0) 0 1 0 16
X[6]=120310

DBG(190831240)> CPU TRACE: 1: 320070 000002107203 (CMPX7 000002,DU) 000002 107(0) 0 1 0 03
X[7]=000002 Carry Zero

DBG(190831244)> CPU TRACE: 1: 320071 000007601204 (TNZ 000007,IC) 000007 601(0) 0 1 0 04

DBG(190831248)> CPU TRACE: 1: 320072 000000235214 (LDA 000000,4) 000000 235(0) 0 1 0 14
DBG(190831248)> CPU FINAL: Read (Actual) Read:       abs address=00120302  readData=010120716001
A=010120716001

DBG(190831252)> CPU TRACE: 1: 320073 000036773200 (LRL 000036) 000036 773(0) 0 1 0 00
A=000000000001 Q=012071600100

DBG(190831256)> CPU TRACE: 1: 320074 000003375207 (ANA 000003,DL) 000003 375(0) 0 1 0 07
A=000000000001 Carry

DBG(190831260)> CPU TRACE: 1: 320075 000003600204 (TZE 000003,IC) 000003 600(0) 0 1 0 04

DBG(190831264)> CPU TRACE: 1: 320076 000000623205 (EAX3 000000,AL) 000000 623(0) 0 1 0 05
X[3]=000001

DBG(190831268)> CPU TRACE: 1: 320077 000006710204 (TRA 000006,IC) 000006 710(0) 0 1 0 04

swtest3:  eax7      0                   see if any switches are set wrongly
          ldx6      switch_discrep-*,ic remember, ABSOLUTE MODE
          ldx5      switch_and-*,ic     ..

DBG(190831272)> CPU TRACE: 1: 320105 000000627200 (EAX7 000000) 000000 627(0) 0 1 0 00
X[7]=000000

DBG(190831276)> CPU TRACE: 1: 320106 000301226204 (LDX6 000301,IC) 000301 226(0) 0 1 0 04
X[6]=120312

DBG(190831280)> CPU TRACE: 1: 320107 000277225204 (LDX5 000277,IC) 000277 225(0) 0 1 0 04
X[5]=120317

swtest4:  lda       0,6                 pick up discrepancy data
          cana      0,5                 any bits on?
          tnz       swerr-*,ic          if so, stop now
          eax5      1,5                 check all switches
          eax6      1,6                 ..
          cmpx7     2,du                was this data from an rsw (2)?
          tnz       swtest5-*,ic        xfer if no
          cmpx3     1,du                yes, is this a DPS8 CPU?
          tze       swtest6-*,ic        xfer if yes

DBG(190831284)> CPU TRACE: 1: 320110 000000235216 (LDA 000000,6) 000000 235(0) 0 1 0 16
A=000000000000

DBG(190831288)> CPU TRACE: 1: 320111 000000315215 (CANA 000000,5) 000000 315(0) 0 1 0 15
A=000000000000 Carry Zero

DBG(190831292)> CPU TRACE: 1: 320112 000013601204 (TNZ 000013,IC) 000013 601(0) 0 1 0 04

DBG(190831296)> CPU TRACE: 1: 320113 000001625215 (EAX5 000001,5) 000001 625(0) 0 1 0 15
X[5]=120320

DBG(190831300)> CPU TRACE: 1: 320114 000001626216 (EAX6 000001,6) 000001 626(0) 0 1 0 16
X[6]=120313

DBG(190831304)> CPU TRACE: 1: 320115 000002107203 (CMPX7 000002,DU) 000002 107(0) 0 1 0 03
X[7]=000000 Neg

DBG(190831308)> CPU TRACE: 1: 320116 000003601204 (TNZ 000003,IC) 000003 601(0) 0 1 0 04

swtest5:  cmpx7     4,du                is this  data from an rsw (4)?
          tze       swtest6-*,ic        yes, we are all done
          eax7      1,7                 ..
          tra       swtest4-*,ic        ..

DBG(190831312)> CPU TRACE: 1: 320121 000004107203 (CMPX7 000004,DU) 000004 107(0) 0 1 0 03
X[7]=000000 Neg

DBG(190831316)> CPU TRACE: 1: 320122 000012600204 (TZE 000012,IC) 000012 600(0) 0 1 0 04

DBG(190831320)> CPU TRACE: 1: 320123 000001627217 (EAX7 000001,7) 000001 627(0) 0 1 0 17
X[7]=000001

DBG(190831324)> CPU TRACE: 1: 320124 777764710204 (TRA 777764,IC) 777764 710(0) 0 1 0 04

swtest4:  lda       0,6                 pick up discrepancy data
          cana      0,5                 any bits on?
          tnz       swerr-*,ic          if so, stop now
          eax5      1,5                 check all switches
          eax6      1,6                 ..
          cmpx7     2,du                was this data from an rsw (2)?
          tnz       swtest5-*,ic        xfer if no
          cmpx3     1,du                yes, is this a DPS8 CPU?
          tze       swtest6-*,ic        xfer if yes

DBG(190831328)> CPU TRACE: 1: 320110 000000235216 (LDA 000000,6) 000000 235(0) 0 1 0 16
A=000000000000

DBG(190831332)> CPU TRACE: 1: 320111 000000315215 (CANA 000000,5) 000000 315(0) 0 1 0 15
DBG(190831332)> CPU FINAL: Read (Actual) Read:       abs address=00120320  readData=757757757757
Zero

DBG(190831336)> CPU TRACE: 1: 320112 000013601204 (TNZ 000013,IC) 000013 601(0) 0 1 0 04

DBG(190831340)> CPU TRACE: 1: 320113 000001625215 (EAX5 000001,5) 000001 625(0) 0 1 0 15
X[5]=120321

DBG(190831344)> CPU TRACE: 1: 320114 000001626216 (EAX6 000001,6) 000001 626(0) 0 1 0 16
X[6]=120314

DBG(190831348)> CPU TRACE: 1: 320115 000002107203 (CMPX7 000002,DU) 000002 107(0) 0 1 0 03
X[7]=000001 Neg

DBG(190831352)> CPU TRACE: 1: 320116 000003601204 (TNZ 000003,IC) 000003 601(0) 0 1 0 04

swtest5:  cmpx7     4,du                is this  data from an rsw (4)?
          tze       swtest6-*,ic        yes, we are all done
          eax7      1,7                 ..
          tra       swtest4-*,ic        ..

DBG(190831356)> CPU TRACE: 1: 320121 000004107203 (CMPX7 000004,DU) 000004 107(0) 0 1 0 03
X[7]=000001 Neg

DBG(190831360)> CPU TRACE: 1: 320122 000012600204 (TZE 000012,IC) 000012 600(0) 0 1 0 04

DBG(190831364)> CPU TRACE: 1: 320123 000001627217 (EAX7 000001,7) 000001 627(0) 0 1 0 17
X[7]=000002

DBG(190831368)> CPU TRACE: 1: 320124 777764710204 (TRA 777764,IC) 777764 710(0) 0 1 0 04

swtest4:  lda       0,6                 pick up discrepancy data
          cana      0,5                 any bits on?
          tnz       swerr-*,ic          if so, stop now
          eax5      1,5                 check all switches
          eax6      1,6                 ..
          cmpx7     2,du                was this data from an rsw (2)?
          tnz       swtest5-*,ic        xfer if no
          cmpx3     1,du                yes, is this a DPS8 CPU?
          tze       swtest6-*,ic        xfer if yes

DBG(190831372)> CPU TRACE: 1: 320110 000000235216 (LDA 000000,6) 000000 235(0) 0 1 0 16
A=000000000000

DBG(190831376)> CPU TRACE: 1: 320111 000000315215 (CANA 000000,5) 000000 315(0) 0 1 0 15
DBG(190831376)> CPU FINAL: Read (Actual) Read:       abs address=00120321  readData=777740000007
Zero

DBG(190831380)> CPU TRACE: 1: 320112 000013601204 (TNZ 000013,IC) 000013 601(0) 0 1 0 04

DBG(190831384)> CPU TRACE: 1: 320113 000001625215 (EAX5 000001,5) 000001 625(0) 0 1 0 15
X[5]=120322

DBG(190831388)> CPU TRACE: 1: 320114 000001626216 (EAX6 000001,6) 000001 626(0) 0 1 0 16
X[6]=120315

DBG(190831392)> CPU TRACE: 1: 320115 000002107203 (CMPX7 000002,DU) 000002 107(0) 0 1 0 03
X[7]=000002 Carry Zero

DBG(190831396)> CPU TRACE: 1: 320116 000003601204 (TNZ 000003,IC) 000003 601(0) 0 1 0 04

DBG(190831400)> CPU TRACE: 1: 320117 000001103203 (CMPX3 000001,DU) 000001 103(0) 0 1 0 03
X[3]=000001 Carry Zero

DBG(190831404)> CPU TRACE: 1: 320120 000014600204 (TZE 000014,IC) 000014 600(0) 0 1 0 04

swtest6:
          eax7      0                   controller port number in X7
ctest1:   lda       controller_data-*,ic  get controllers online
          tpl       2,ic                if this one offline, skip reference
          rccl      0,7                 if controller port not enabled, get onc fault
          nop       0,du                allow possible onc to "take"
          nop       0,du                ..
          eax7      32768,7             step to next port
          lda       controller_data-*,ic  get controllers online
          als       1                   shift to next controller
          sta       controller_data-*,ic  replace data
          tnz       ctest1-*,ic         loop if more to do

          scu       cudata-*,ic         store control unit
          lda       scu.apu.pt_on+scu.apu.sd_on,dl  AM's on?
          cnaa      cudata-*+scu.apu_stat_word,ic
          tnz       amerr-*,ic          if not, stop

          ldbr      new_dbr-*,ic        load the DBR
          tra       continue-*,ic*      enter appending mode

DBG(190831408)> CPU TRACE: 1: 320134 000000627200 (EAX7 000000) 000000 627(0) 0 1 0 00
X[7]=000000

DBG(190831412)> CPU TRACE: 1: 320135 000253235204 (LDA 000253,IC) 000253 235(0) 0 1 0 04
A=740000000000 Carry Neg

DBG(190831416)> CPU TRACE: 1: 320136 000002605204 (TPL 000002,IC) 000002 605(0) 0 1 0 04

DBG(190831420)> CPU TRACE: 1: 320137 000000633217 (RCCL 000000,7) 000000 633(0) 0 1 0 17
X[7]=000000
A=000000150303 Q=722234063044

DBG(190831424)> CPU TRACE: 1: 320140 000000011203 (NOP 000000,DU) 000000 011(0) 0 1 0 03

DBG(190831428)> CPU TRACE: 1: 320141 000000011203 (NOP 000000,DU) 000000 011(0) 0 1 0 03

DBG(190831432)> CPU TRACE: 1: 320142 100000627217 (EAX7 100000,7) 100000 627(0) 0 1 0 17
X[7]=100000

DBG(190831436)> CPU TRACE: 1: 320143 000245235204 (LDA 000245,IC) 000245 235(0) 0 1 0 04
A=740000000000

DBG(190831440)> CPU TRACE: 1: 320144 000001735200 (ALS 000001) 000001 735(0) 0 1 0 00
A=700000000000

DBG(190831444)> CPU TRACE: 1: 320145 000243755204 (STA 000243,IC) 000243 755(0) 0 1 0 04

DBG(190831448)> CPU TRACE: 1: 320146 777767601204 (TNZ 777767,IC) 777767 601(0) 0 1 0 04

DBG(190831452)> CPU TRACE: 1: 320135 000253235204 (LDA 000253,IC) 000253 235(0) 0 1 0 04
A=700000000000 Neg

DBG(190831456)> CPU TRACE: 1: 320136 000002605204 (TPL 000002,IC) 000002 605(0) 0 1 0 04

DBG(190831460)> CPU TRACE: 1: 320137 000000633217 (RCCL 000000,7) 000000 633(0) 0 1 0 17

DBG(190831464)> CPU TRACE: 1: 320140 000000011203 (NOP 000000,DU) 000000 011(0) 0 1 0 03

DBG(190831468)> CPU TRACE: 1: 320141 000000011203 (NOP 000000,DU) 000000 011(0) 0 1 0 03

DBG(190831472)> CPU TRACE: 1: 320142 100000627217 (EAX7 100000,7) 100000 627(0) 0 1 0 17
X[7]=200000

DBG(190831476)> CPU TRACE: 1: 320143 000245235204 (LDA 000245,IC) 000245 235(0) 0 1 0 04
A=700000000000

DBG(190831480)> CPU TRACE: 1: 320144 000001735200 (ALS 000001) 000001 735(0) 0 1 0 00
A=600000000000

DBG(190831484)> CPU TRACE: 1: 320145 000243755204 (STA 000243,IC) 000243 755(0) 0 1 0 04

DBG(190831488)> CPU TRACE: 1: 320146 777767601204 (TNZ 777767,IC) 777767 601(0) 0 1 0 04

DBG(190831492)> CPU TRACE: 1: 320135 000253235204 (LDA 000253,IC) 000253 235(0) 0 1 0 04
A=600000000000

DBG(190831496)> CPU TRACE: 1: 320136 000002605204 (TPL 000002,IC) 000002 605(0) 0 1 0 04

DBG(190831500)> CPU TRACE: 1: 320137 000000633217 (RCCL 000000,7) 000000 633(0) 0 1 0 17

DBG(190831504)> CPU TRACE: 1: 320140 000000011203 (NOP 000000,DU) 000000 011(0) 0 1 0 03

DBG(190831508)> CPU TRACE: 1: 320141 000000011203 (NOP 000000,DU) 000000 011(0) 0 1 0 03

DBG(190831512)> CPU TRACE: 1: 320142 100000627217 (EAX7 100000,7) 100000 627(0) 0 1 0 17
X[7]=300000

DBG(190831516)> CPU TRACE: 1: 320143 000245235204 (LDA 000245,IC) 000245 235(0) 0 1 0 04
A=600000000000

DBG(190831520)> CPU TRACE: 1: 320144 000001735200 (ALS 000001) 000001 735(0) 0 1 0 00
A=400000000000

DBG(190831524)> CPU TRACE: 1: 320145 000243755204 (STA 000243,IC) 000243 755(0) 0 1 0 04

DBG(190831528)> CPU TRACE: 1: 320146 777767601204 (TNZ 777767,IC) 777767 601(0) 0 1 0 04

DBG(190831532)> CPU TRACE: 1: 320135 000253235204 (LDA 000253,IC) 000253 235(0) 0 1 0 04
A=400000000000

DBG(190831536)> CPU TRACE: 1: 320136 000002605204 (TPL 000002,IC) 000002 605(0) 0 1 0 04

DBG(190831540)> CPU TRACE: 1: 320137 000000633217 (RCCL 000000,7) 000000 633(0) 0 1 0 17

DBG(190831544)> CPU TRACE: 1: 320140 000000011203 (NOP 000000,DU) 000000 011(0) 0 1 0 03

DBG(190831548)> CPU TRACE: 1: 320141 000000011203 (NOP 000000,DU) 000000 011(0) 0 1 0 03

DBG(190831552)> CPU TRACE: 1: 320142 100000627217 (EAX7 100000,7) 100000 627(0) 0 1 0 17
X[7]=400000

DBG(190831556)> CPU TRACE: 1: 320143 000245235204 (LDA 000245,IC) 000245 235(0) 0 1 0 04
A=400000000000

DBG(190831560)> CPU TRACE: 1: 320144 000001735200 (ALS 000001) 000001 735(0) 0 1 0 00
A=000000000000

DBG(190831564)> CPU TRACE: 1: 320145 000243755204 (STA 000243,IC) 000243 755(0) 0 1 0 04

DBG(190831568)> CPU TRACE: 1: 320146 777767601204 (TNZ 777767,IC) 777767 601(0) 0 1 0 04

DBG(190831572)> CPU TRACE: 1: 320147 000211657204 (SCU 000211,IC) 000211 657(0) 0 1 0 04
DBG(190831572)> CPU FINAL: Write(Actual) Write:      abs address=00320360 writeData=000000450010
DBG(190831572)> CPU FINAL: Write(Actual) Write:      abs address=00320361 writeData=000000000001
DBG(190831572)> CPU FINAL: Write(Actual) Write:      abs address=00320362 writeData=000000000100
DBG(190831572)> CPU FINAL: Write(Actual) Write:      abs address=00320363 writeData=000000000000
DBG(190831572)> CPU FINAL: Write(Actual) Write:      abs address=00320364 writeData=320147500220
DBG(190831572)> CPU FINAL: Write(Actual) Write:      abs address=00320365 writeData=000211000000
DBG(190831572)> CPU FINAL: Write(Actual) Write:      abs address=00320366 writeData=000211657204
DBG(190831572)> CPU FINAL: Write(Actual) Write:      abs address=00320367 writeData=000000000000

DBG(190831576)> CPU TRACE: 1: 320150 050000235207 (LDA 050000,DL) 050000 235(0) 0 1 0 07
A=000000050000

DBG(190831580)> CPU TRACE: 1: 320151 000207215204 (CNAA 000207,IC) 000207 215(0) 0 1 0 04
DBG(190831580)> CPU FINAL: Read (Actual) Read:       abs address=00320360  readData=000000450010
Carry Zero

DBG(190831584)> CPU TRACE: 1: 320152 000011601204 (TNZ 000011,IC) 000011 601(0) 0 1 0 04

DBG(190831588)> CPU TRACE: 1: 320153 000215232204 (LDBR 000215,IC) 000215 232(0) 0 1 0 04

DBG(190831588)> CPU FINAL: Read (Actual) Read:       abs address=00320370  readData=000524470004
DBG(190831588)> CPU FINAL: Read (Actual) Read:       abs address=00320371  readData=000775100000
DBG(190831588)> CPU APPENDING: ldbr 0 -> SDWAM/PTWAM[*].F, i -> SDWAM/PTWAM[i].USE, DSBR.ADDR 052447, DSBR.BND 077, DSBR.U 00, DSBR.STACK 00

DBG(190831592)> CPU TRACE: 1: 320154 000222710224 (TRA 000222,IC*) 000222 710(0) 0 1 1 04
DBG(190831592)> CPU APPENDING: doITS/ITP: YPair= 000061000043 000177000000
DBG(190831592)> CPU APPENDING: ITS Pair: SEGNO=61 RN=0 WORDNO=177 BITNO=0 MOD=0
DBG(190831592)> CPU APPENDING: ITS Pair Ring: RN 0 RSDWH_R1 0 TRR 0 max 0

DBG(190831600)> CPU TRACE: 1: 000404 000034000043 (??? 000034,ITS) 000034 000(0) 0 0 2 03

Hmm.. Going into appending mode via ITS instead of B29…. didn't work.

Fixed TRA to appending mode…

The second CPU appears to start fine.

The bootload CPU sees the 2nd CPU start, and apparently gets lost…

Tracing the start_cpu code:

/* Now give back the double pages we borrowed */

               do i = 0 to 7;
                    base = remember (i);
                    if base > 0 then do;
                         call freecore (base);
                         call freecore (base + 1);
                    end;
               end;

               string (tsdw1) = "0"b;
               call privileged_mode_ut$swap_sdw (abs_seg_p, addr (tsdw1));
               if rcode ^= 0 then do;                       /* If an error occurred ... */
                    call stop_cpu$destroy_1 (tag, tcode);   /* Clean up the mess we made. */
                    return;
               end;
          end;                                              /* Mask the discrepancy data. */

                         call freecore (base);

002072  aa  6 00171 3521 00   epp2      pr6|121             base
002073  aa  6 00250 2521 00   spri2     pr6|168
002074  aa  6 00246 6211 00   eax1      pr6|166
002075  aa   004000 4310 07   fld       2048,dl
002076  aa  6 00044 3701 20   epp4      pr6|36,*
002077  la  4 00152 3521 20   epp2      pr4|106,*           freecore
002100  aa  0 00623 7001 00   tsx0      pr0|403             call_ext_out

DBG(190843727)> CPU0 TRACE: 00132:004472 0 600171352100 (EPP2 PR6|171) 600171 352(0) 1 0 0 00
DBG(190843733)> CPU0 TRACE: 00132:004473 0 600250252100 (SPRI2 PR6|250) 600250 252(0) 1 0 0 00
DBG(190843739)> CPU0 TRACE: 00132:004474 0 600246621100 (EAX1 PR6|246) 600246 621(0) 1 0 0 00
DBG(190843745)> CPU0 TRACE: 00132:004475 0 004000431007 (FLD 004000,DL) 004000 431(0) 0 0 0 07
DBG(190843751)> CPU0 TRACE: 00132:004476 0 600044370120 (EPP4 PR6|44,N*) 600044 370(0) 1 0 1 00
DBG(190843757)> CPU0 TRACE: 00132:004477 0 400024352120 (EPP2 PR4|24,N*) 400024 352(0) 1 0 1 00
DBG(190843763)> CPU0 TRACE: 00132:004500 0 000623700100 (TSX0 PR0|623) 000623 700(0) 1 0 0 00

Never returns from freecore.

I wonder if the 2nd CPU is contraindicated during install. Add 2nd CPU to yoyodyne.ini?

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