CAC 2015-11-08

SCU interrupt masks.

SCR configuration register program settable bits mask:

dcl  SCR_CFG2_PROGRAM_MASK bit (72) aligned int static options (constant)
        init ("777774037777777000077417"b3);                /* program settable bits in config register       */

dcl 1 scr_cfg2 based (scrp) aligned,                        /* configuration data for 4MW SCU */

   (2 mask_a_assign bit (9),                                /* interrupt mask "A" port assignment
                                                               400 => assigned to port 0
                                                               .
                                                               .
                                                               002 => assigned to port 7
                                                               001 => mask off */
    2 size bit (3),                                         /* size of lower store */
    2 a_online bit (1),                                     /* 1 => store A online */
    2 a1_online bit (1),                                    /* 1 => store A1 online */
    2 b_online bit (1),                                     /* 1 => store B online */
    2 b1_online bit (1),                                    /* 1 => store B1 online */
    2 port_no bit (4),                                      /* requester's port number */
    2 pad1 bit (1),
    2 mode bit (1),                                         /* 1 => programmable mode */
    2 nea_enabled bit (1),                                  /* 1 => non-existent address logic enabled */
    2 nea bit (7),                                          /* 001 => 32K, 002 => 64K, 003 => 96K, etc. */
    2 int bit (1),                                          /* 1 => stores are internally interlaced */
    2 lwr bit (1),                                          /* 1 => store B is low */
    2 port_mask_0_3 bit (4),                                /* 1 => corresponding port enabled */

    2 mask_b_assign bit (9),                                /* interrupt mask "B" port assignment */
    2 pad2 bit (12),
    2 cyclic_prior bit (7),                                 /* cyclic port priority switches */
    2 pad3 bit (4),
    2 port_mask_4_7 bit (4)) unal;                          /* 1 => corresponding port enabled */

777774037777777000077417
111111111  mask_a_assign
111   size         
1   a_online
1   a1_online
1   b_online
1   b1_online
0000 requestor's port number
0    pad
0   mode
1   nea_enabled
1111111 nea
1  int
1  lwr
1111 port_mask_0_3
111111111 mask_b_assign
000000000000 pad2
1111111 cyclic
0000 pad3
1111 port_mask_4_7

sscr 0 enable 10000011 cyclic 000 nea 200 onl 14 sz 7 il 0 lwr 0 A 7 B 6
rscr 002761660014 004000000001  14 01
CONSOLE: ALERT
^G1028.7  scr_util: error setting configuration register. SCU A must be set manually
1028.7  Set the following switches on SCU A
1028.7  
            --PORT ENABLE--  --CYCLIC PRIORITY---
            0 1 2 3 4 5 6 7  0/1 1/2 2/3 3/4 4/5 5/6 6/7
        ON  X           X X                              
        OFF   X X X X X       X   X   X   X   X   X   X  
1028.7  
        NON-EXISTENT ADDRESS
                 2 3 4 5 6 7 8
        ON  X  1               
        OFF    0 X X X X X X X 
1028.7  
        STORE A  A1 B  B1
        ON    X  X        
        OFF         X  X  
1028.7  
        LWR STORE SIZE - 7
        INTERLACE - OFF
        LWR STORE - A
        MASK A - 7
        MASK B - 6

002761660014 004000000001 

000000010  maska  7
111 size 7
1100  a, a1 online
0111 received port number
0 pad
1 mod programmable
10000000 NEA enabled, addr 0
0 interlace off
0 lwr A
1100 pmr 

000000100 maskb 6
000000000000 pad
0000000 cyclic
0000 pad 
0001 pmr

DBG(382293367)> CPU TRACE: 00132:004531 bound_hc_reconfig:start_cpu+02131^M
DBG(382293367)> CPU TRACE:       518         call privileged_mode_ut$swap_sdw (abs_seg_p, addr (tsdw1));^M
DBG(382293367)> CPU TRACE: 00132:004531 0 000623700100 (TSX0 PR0|623) 000623 700(0) 1 0 0 00^M
DBG(382293367)> CPU APPENDING: Read (Actual) Read:  iefpFinalAddress=77450561  readData=026134710000^M

DBG(382293507)> CPU TRACE: RTCD 00132:004532^M
DBG(382293507)> CPU TRACE: RTCD PPR.PRR 0 PPR.P 0^M
DBG(382293507)> CPU REGDUMPAQI: A=000000000000 Q=000000000000 IR:~BAR Carry ^M

DBG(382293509)> CPU APPENDING: Read (Actual) Read:  iefpFinalAddress=75102532  readData=600032373520^M

DBG(382293511)> CPU TRACE: 00132:004532 bound_hc_reconfig:start_cpu+02132^M
DBG(382293511)> CPU TRACE:       519         if rcode ^= 0 then do;                       /* If an error occurred ... */^M
DBG(382293511)> CPU TRACE: 00132:004532 0 600032373520 (EPP7 PR6|32,N*) 600032 373(1) 1 0 1 00^M
DBG(382293511)> CPU APPENDING: Read (Actual) Read:  iefpFinalAddress=77167512  readData=000062000043^M
DBG(382293511)> CPU APPENDING: Read (Actual) Read:  iefpFinalAddress=77167513  readData=001166000000^M
DBG(382293511)> CPU REGDUMPAQI: A=000000000000 Q=000000000000 IR:~BAR Carry ^M

DBG(382293513)> CPU APPENDING: Read (Actual) Read:  iefpFinalAddress=75102533  readData=700004236120^M

DBG(382293515)> CPU TRACE: 00132:004533 bound_hc_reconfig:start_cpu+02133^M
DBG(382293515)> CPU TRACE:       519         if rcode ^= 0 then do;                       /* If an error occurred ... */^M
DBG(382293515)> CPU TRACE: 00132:004533 0 700004236120 (LDQ PR7|4,N*) 700004 236(0) 1 0 1 00^M
DBG(382293515)> CPU APPENDING: Read (Actual) Read:  iefpFinalAddress=77167172  readData=000062000043^M
DBG(382293515)> CPU APPENDING: Read (Actual) Read:  iefpFinalAddress=77167173  readData=001076000000^M
DBG(382293515)> CPU APPENDING: Read (Actual) Read:  iefpFinalAddress=77167076  readData=000000000001^M
DBG(382293515)> CPU REGDUMPAQI: A=000000000000 Q=000000000001 IR:~BAR Carry ^M