CAC 2012-12-11
istart crash
DBG(231253)> CPU TRACE: 55535:156400 STZ 400,1
DBG(231253)> CPU CAF: CAF entry: I 0 T 1 D 400
DBG(231253)> CPU REG: rX1 RD 077400
DBG(231253)> CPU CAF: after getT ct 0 wt 77400
DBG(231253)> CPU CAF: w6 00000
DBG(231253)> CPU DEBUG: addAddr32 wx 77400 cx 0 wy 00000 cy 4
DBG(231253)> CPU DEBUG: addAddr32 w 77400
DBG(231253)> CPU DEBUG: addAddr32 c 7
fault 00445 : addAddr32(): illegal charAddr
156400
001 101 110 100 000 000
I 0
T 1
OP 56
D 400
Bug in the CAF code.
The timers
rem ***********************************************************
rem * check if timer is enabled and running
rem ***********************************************************
rem
lda a.u009-*,* (etmb) get current value of elapsed timer
ldq l.v002-* (=1000) get two millisecond counter
iaq -1 wait two milliseconds
tnz -1
cmpa a.u009-*,* (etmb) check and see if timer changed
tnz itl230-* yes-ok
tra 1,* no. error...timer not enabled
ind stop02
l.v002 dec 1000 two milliseconds in inst xec time
Simple CPU instructions take 1 us. Assuming Nyquist sampling above, the elapsed timer runs at 1 ms.
rem ***********************************************************
rem * check to make sure interval timer switch is set
rem * to click every msec and not every 64th of a msec
rem ***********************************************************
rem
itl230 null
ila 2 set timer to go off in 2 msec
ldq itl250-* ..
tsy a.v018-*,* (setclk)
ldq l.v001-* (=250) get half millisecond counter
iaq -1 wait half millisecond
tnz -1 ..
stz itl250-* if we finished counting, timer is set to click
rem every msec. set flag and wait for timer to go off
dis
itl240 ind stop12
itl250 ind *+1 addr of place to go on timer interrupt
ind **
szn itl250-* did we finish counting above?
tnz itl240-*,* no - timer sw is wrong - inform cs
The interval timer is programmable, but MCS expects 1 ms.
************************************************************************
* setclk -- set interval timer
* rstclk -- reset interval timer
*
* entry -- setclk
*
* lda (number milliseconds)
* ldq (return address on runout)
* tsy setclk-*
*
* entry -- rstclk
*
* tsy rstclk-*
***********************************************************************
rem
setclk ind **
sti scindc-* save io select register
sel tmch select clock channel
cioc scoff-* turn clock off
sta scvalu-*,* store time value
stq sciv-*,* store user's iv
cioc scon-* turn clock on
ldi scindc-* restor io select reg <?><?><?><?><?><?><?><?>
tra setclk-*,* return
rem
rem
rem
rstclk ind **
sti scindc-* save io select register
sel tmch select clock channel
cioc scoff-* turn clock off
ldi scindc-* restore io select register <?><?><?><?><?>
tra rstclk-*,* return
rem
rem
rem
even
scon oct 0,0
scoff oct 0,010000
scvalu ind itmb interval timer mailbox address
sciv ind tmro interval timer runout iv address
scindc bss 1
msg12 aci 17,timer switch set to 64 khz, s/b 1
rem *********************************************************
rem * setup the interval and elapsed timers
rem *********************************************************
rem
stz a.m006-*,* (itmb) interval timer value = 0
lda a.m007-* (timrjt) interval timer jump table
sta a.m008-*,* (tmro) timer interrupt vector
lda a.m021-*,* (etrint) get elapsed timer default value
sta a.m009-*,* (etmb)
lda a.m010-* (etrip) elapsed timer interrupt handler
sta a.m011-*,* (etr) timer interrupt vector
tsy a.m015-*,* (rstclk) turn clock off
rem
ldaq sdqdat-* schedule dummy rtn to kick off timer
tsy a.m026-*,* (dspqur) since clock doesnt start til it is used
rem now run the idle loop for one metering interval
rem to establish a counter value for an idle interval
rem
lda a.u017-* addr (itl215)
sta a.u018-*,* (etr) direct timer interrupt to here
ila 0 get negative interval size to set timer
sba a.u019-*,* idlint
sta a.u009-*,* etmb
tra a.u020-*,* (idloop) run the idle loop till timer goes off
rem
itl215 ind ** elapsed timer runout comes here
ldaq a.u021-*,* idlcnt
staq a.u022-*,* (idlmax) this is maximum value
staq a.u023-*,* (idlmin) and also minimum so far
lda ignrad-* now ignore timer interrupts again
sta a.u018-*,* etr
ila 0 and clear the counter
ilq 0
staq a.u021-*,* idlcnt
page revision: 1, last edited: 11 Dec 2021 23:26